{ "Name": "eeprom-ex", "ProjectVersion": "1.0.0.0", "Versions": {}, "EnableVersionControl": false, "Presets": { "$type": "System.Collections.ObjectModel.Collection`1[[System.String, mscorlib]], mscorlib", "$values": [] }, "Diagram": { "$type": "AnalogDevices.TypeDefinitions.Dom.SsprjDom.Internals.SystemShapeModel, TypeDefinitions", "Uid": "Diagram_0", "WritableProperties": {}, "WritableCommChannels": [ { "$type": "AnalogDevices.TypeDefinitions.Dom.SsprjDom.Internals.CommChannelModel, TypeDefinitions", "WritableProperties": {}, "Uid": "USB_0", "Name": "USB", "PluginName": "AnalogDevices.Plugins.CommunicationChannels.USBChannel_v1.0.0.0", "InterfaceType": "AnalogDevices.TypeDefinitions.Plugins.ICommChannel", "LinkReference": { "$type": "System.Collections.ObjectModel.Collection`1[[System.String, mscorlib]], mscorlib", "$values": [ "Link_6" ] }, "ChannelReference": { "$type": "System.Collections.ObjectModel.Collection`1[[System.String, mscorlib]], mscorlib", "$values": [] }, "ShapeReference": { "$type": "System.Collections.ObjectModel.Collection`1[[System.String, mscorlib]], mscorlib", "$values": [] } }, { "$type": "AnalogDevices.TypeDefinitions.Dom.SsprjDom.Internals.CommChannelModel, TypeDefinitions", "WritableProperties": {}, "Uid": "I2C_0", "Name": "I2C", "PluginName": "AnalogDevices.Plugins.Channels.ControlChannel_v1.0.0.0", "InterfaceType": "AnalogDevices.TypeDefinitions.Plugins.ICommChannel", "LinkReference": { "$type": "System.Collections.ObjectModel.Collection`1[[System.String, mscorlib]], mscorlib", "$values": [ "Link_7" ] }, "ChannelReference": { "$type": "System.Collections.ObjectModel.Collection`1[[System.String, mscorlib]], mscorlib", "$values": [] }, "ShapeReference": { "$type": "System.Collections.ObjectModel.Collection`1[[System.String, mscorlib]], mscorlib", "$values": [] } } ], "WritableNetworks": [], "WritableSdks": [], "CanvasSize": { "Height": 1920.0, "Width": 1080.0 }, "WritableChannels": [], "WritableShapes": [ { "PluginName": "AnalogDevices.Plugins.Controllers.PC_v1.0.0.0", "Name": "PC", "InterfaceType": "AnalogDevices.TypeDefinitions.Plugins.IController", "Uid": "PC_0", "WritableProperties": { "IsRemovable": false, "RestrictShape": false, "BoardKey": "", "IsLocked": false, "EncryptedString": "" }, "Angle": 0.0, "Position": { "X": -209.41176470588243, "Y": 231.76470588235293 }, "Size": { "Height": 113.0, "Width": 116.0 }, "Label": "PC_0", "WritableChannels": [], "WritableShapes": [], "WriteableLinks": [], "AltShapes": [], "PropertyPresets": {} }, { "PluginName": "AnalogDevices.Plugins.Platforms.CustomPlatform_v1.0.0.0", "Name": "Custom Platform", "InterfaceType": "AnalogDevices.TypeDefinitions.Plugins.IPlatform", "Uid": "CustomPlatform_0", "WritableProperties": { "IsRemovable": true, "RestrictShape": false, "BoardKey": "", "IsLocked": false, "EncryptedString": "", "CustomPlatformPins": { "$type": "System.Collections.Generic.List`1[[AnalogDevices.TypeDefinitions.Plugins.PinDefinition, TypeDefinitions]], mscorlib", "$values": [ { "Name": "SPI Slave Port(EEPROM_0)", "PinType": 1, "DataType": 0, "IsTarget": true, "IsSource": false, "RelativePosition": { "X": 0.0, "Y": 0.33333333333333331 }, "IsEnabled": true, "ChannelName": "AnalogDevices.Plugins.Channels.ControlChannel_v1.0.0.0", "type": "AnalogDevices.TypeDefinitions.Plugins.ICommChannel, TypeDefinitions, Version=2.2.0.1, Culture=neutral, PublicKeyToken=null", "TransferFunction": null }, { "Name": "I2C Slave Port", "PinType": 2, "DataType": 0, "IsTarget": true, "IsSource": false, "RelativePosition": { "X": 0.0, "Y": 0.66666666666666663 }, "IsEnabled": true, "ChannelName": "AnalogDevices.Plugins.Channels.ControlChannel_v1.0.0.0", "type": "AnalogDevices.TypeDefinitions.Plugins.ICommChannel, TypeDefinitions, Version=2.2.0.1, Culture=neutral, PublicKeyToken=null", "TransferFunction": null } ] }, "MergeI2CPins": true, "I2CPins": { "$type": "System.Collections.Generic.List`1[[AnalogDevices.TypeDefinitions.Plugins.PinDefinition, TypeDefinitions]], mscorlib", "$values": [ { "Name": "I2C Slave Port(ADAU1452_0)", "PinType": 2, "DataType": 0, "IsTarget": true, "IsSource": false, "RelativePosition": { "X": 0.0, "Y": 0.5 }, "IsEnabled": true, "ChannelName": "AnalogDevices.Plugins.Channels.ControlChannel_v1.0.0.0", "type": "AnalogDevices.TypeDefinitions.Plugins.ICommChannel, TypeDefinitions, Version=2.2.0.1, Culture=neutral, PublicKeyToken=null", "TransferFunction": null } ] }, "CustomPlatformColor": "#313030", "PlatformName": "Custom Platform" }, "Angle": 0.0, "Position": { "X": 260.29411764705878, "Y": 244.41176470588232 }, "Size": { "Height": 133.0, "Width": 133.0 }, "Label": "CustomPlatform_0", "WritableChannels": [], "WritableShapes": [ { "PluginName": "AnalogDevices.Plugins.Processors.ADAU1452_v1.0.0.0", "Name": "ADAU1452", "InterfaceType": "AnalogDevices.TypeDefinitions.Plugins.IProcessor", "Uid": "ADAU1452_0", "WritableProperties": { "IsRemovable": true, "RestrictShape": false, "BoardKey": "", "IsLocked": false, "EncryptedString": "", "WriteCompilation": true, "CheckCompilation": true, "EraseMemory": true, "ProcessorName": "ADAU1452", "SlavePort": "I2C", "I2CSlaveAddress": "0x70", "MasterControlPortEnable": false, "MasterControlPort": "SPI", "I2CSlavePortPinLocation": "Left", "WriteThroughDSPPerformed": false, "SPISlavePortPinLocation": "Left", "SPORTTxPinLocation": "Right", "SPORTRxPinLocation": "Right", "ASRC_LOCK_reg_ASRC0L": "Locked", "ASRC_LOCK_reg_ASRC1L": "Locked", "ASRC_LOCK_reg_ASRC2L": "Locked", "ASRC_LOCK_reg_ASRC3L": "Locked", "ASRC_LOCK_reg_ASRC4L": "Locked", "ASRC_LOCK_reg_ASRC5L": "Locked", "ASRC_LOCK_reg_ASRC6L": "Locked", "ASRC_LOCK_reg_ASRC7L": "Locked", "ASRC_LOCK_regRESERVED0 Reserved": 0, "ASRC_MUTE_reg_ASRC0M": "Unmuted", "ASRC_MUTE_reg_ASRC1M": "Unmuted", "ASRC_MUTE_reg_ASRC2M": "Unmuted", "ASRC_MUTE_reg_ASRC3M": "Unmuted", "ASRC_MUTE_reg_ASRC4M": "Unmuted", "ASRC_MUTE_reg_ASRC5M": "Unmuted", "ASRC_MUTE_reg_ASRC6M": "Unmuted", "ASRC_MUTE_reg_ASRC7M": "Unmuted", "ASRC_MUTE_reg_ASRC_RAMP0": "Enabled", "ASRC_MUTE_reg_ASRC_RAMP1": "Enabled", "ASRC_MUTE_reg_LOCKMUTE": "Do not mute", "ASRC_MUTE_regRESERVED1 Reserved": 0, "ASRC0_RATIO_reg_ASRC_RATIO": 0, "ASRC1_RATIO_reg_ASRC_RATIO": 0, "ASRC2_RATIO_reg_ASRC_RATIO": 0, "ASRC3_RATIO_reg_ASRC_RATIO": 0, "ASRC4_RATIO_reg_ASRC_RATIO": 0, "ASRC5_RATIO_reg_ASRC_RATIO": 0, "ASRC6_RATIO_reg_ASRC_RATIO": 0, "ASRC7_RATIO_reg_ASRC_RATIO": 0, "ADC_READ0_reg_ADC_VALUE": 0, "ADC_READ1_reg_ADC_VALUE": 0, "ADC_READ2_reg_ADC_VALUE": 0, "ADC_READ3_reg_ADC_VALUE": 0, "ADC_READ4_reg_ADC_VALUE": 0, "ADC_READ5_reg_ADC_VALUE": 0, "PLL_WATCHDOG_reg_PLL_WATCHDOG": "PLL watchdog enabled", "PLL_WATCHDOG_regRESERVED8 Reserved": 0, "CLK_GEN1_M_reg_CLOCKGEN1_M": 6, "CLK_GEN1_M_regRESERVED9 Reserved": 0, "CLK_GEN1_N_reg_CLOCKGEN1_N": 1, "CLK_GEN1_N_regRESERVED10 Reserved": 0, "CLK_GEN2_M_reg_CLOCKGEN2_M": 9, "CLK_GEN2_M_regRESERVED11 Reserved": 0, "CLK_GEN2_N_reg_CLOCKGEN2_N": 1, "CLK_GEN2_N_regRESERVED12 Reserved": 0, "CLK_GEN3_M_reg_CLOCKGEN3_M": 0, "CLK_GEN3_N_reg_CLOCKGEN3_N": 0, "CLK_GEN3_SRC_reg_FREF_PIN": "FREF comes from SPDIF receiver", "CLK_GEN3_SRC_reg_CLK_GEN3_SRC": "Needs N/M ratio", "CLK_GEN3_SRC_regRESERVED13 Reserved": 0, "CLK_GEN3_LOCK_reg_GEN3_LOCK": "Not locked", "CLK_GEN3_LOCK_regRESERVED14 Reserved": 0, "START_PULSE_reg_START_PULSE": "Base_Fs (48 kHz for 48 kHz base sample rate)", "START_PULSE_regRESERVED16 Reserved": 0, "KILL_CORE_reg_KILL_CORE": "Core not killed", "KILL_CORE_regRESERVED18 Reserved": 0, "START_ADDRESS_reg_START_ADDRESS": 0, "PANIC_CLEAR_reg_PANIC_CLEAR": "Panic manager not cleared", "PANIC_CLEAR_regRESERVED21 Reserved": 0, "PANIC_PARITY_MASK_reg_ASRC0_MASK": "Do not report ASRC0 parity mask errors", "PANIC_PARITY_MASK_reg_ASRC1_MASK": "Do not report ASRC1 parity mask errors", "PANIC_PARITY_MASK_reg_PM0_MASK": "Report PM0 parity mask errors", "PANIC_PARITY_MASK_reg_PM1_MASK": "Report PM1 parity mask errors", "PANIC_PARITY_MASK_reg_DM0_BANK0_MASK": "Report DM0_BANK0 parity mask errors", "PANIC_PARITY_MASK_reg_DM0_BANK1_MASK": "Report DM0_BANK1 parity mask errors", "PANIC_PARITY_MASK_reg_DM0_BANK2_MASK": "Report DM0_BANK2 parity mask errors", "PANIC_PARITY_MASK_reg_DM0_BANK3_MASK": "Report DM0_BANK3 parity mask errors", "PANIC_PARITY_MASK_reg_DM1_BANK0_MASK": "Report DM1_BANK0 parity mask errors", "PANIC_PARITY_MASK_reg_DM1_BANK1_MASK": "Report DM1_BANK1 parity mask errors", "PANIC_PARITY_MASK_reg_DM1_BANK2_MASK": "Report DM1_BANK2 parity mask errors", "PANIC_PARITY_MASK_reg_DM1_BANK3_MASK": "Report DM1_BANK3 parity mask errors", "PANIC_PARITY_MASK_regRESERVED22 Reserved": 0, "PANIC_SOFTWARE_MASK_reg_PANIC_SOFTWARE": "Report software errors", "PANIC_SOFTWARE_MASK_regRESERVED23 Reserved": 0, "PANIC_WD_MASK_reg_PANIC_WD": "Report watchdog errors", "PANIC_WD_MASK_regRESERVED24 Reserved": 0, "PANIC_STACK_MASK_reg_PANIC_STACK": "Report stack errors", "PANIC_STACK_MASK_regRESERVED25 Reserved": 0, "PANIC_LOOP_MASK_reg_PANIC_LOOP": "Report loop errors", "PANIC_LOOP_MASK_regRESERVED26 Reserved": 0, "PANIC_FLAG_reg_PANIC_FLAG": "No error", "PANIC_FLAG_regRESERVED27 Reserved": 0, "PANIC_CODE_reg_ERR_ASRC0": "No error in ASRC0", "PANIC_CODE_reg_ERR_ASRC1": "No error in ASRC1", "PANIC_CODE_reg_ERR_PM0": "No error in PM0", "PANIC_CODE_reg_ERR_PM1": "No error in PM1", "PANIC_CODE_reg_ERR_DM0B0": "No error in DM0 Bank 0", "PANIC_CODE_reg_ERR_DM0B1": "No error in DM0 Bank 1", "PANIC_CODE_reg_ERR_DM0B2": "No error in DM0 Bank 2", "PANIC_CODE_reg_ERR_DM0B3": "No error in DM0 Bank 3", "PANIC_CODE_reg_ERR_DM1B0": "No error in DM1 Bank 0", "PANIC_CODE_reg_ERR_DM1B1": "No error in DM1 Bank 1", "PANIC_CODE_reg_ERR_DM1B2": "No error in DM1 Bank 2", "PANIC_CODE_reg_ERR_DM1B3": "No error in DM1 Bank 3", "PANIC_CODE_reg_ERR_WATCHDOG": "No error from the watchdog counter", "PANIC_CODE_reg_ERR_STACK": "No error from the stack overrun", "PANIC_CODE_reg_ERR_LOOP": "No error from the loop overrun", "PANIC_CODE_reg_ERR_SOFT": "No error from the software panic", "EXECUTE_COUNT_reg_EXECUTE_COUNT": 0, "WATCHDOG_MAXCOUNT_reg_WD_MAXCOUNT": 0, "WATCHDOG_MAXCOUNT_regRESERVED28 Reserved": 0, "WATCHDOG_PRESCALE_reg_WD_PRESCALE": "Increment every 64 clock cycles", "WATCHDOG_PRESCALE_regRESERVED29 Reserved": 0, "BLOCKINT_EN_reg_BLOCKINT_EN": "Disable block interrupts", "BLOCKINT_EN_regRESERVED30 Reserved": 0, "BLOCKINT_VALUE_reg_BLOCKINT_VALUE": 0, "PROG_CNTR0_reg_PROG_CNTR_MSB": 0, "PROG_CNTR0_regRESERVED31 Reserved": 0, "PROG_CNTR1_reg_PROG_CNTR_LSB": 0, "PROG_CNTR_CLEAR_reg_PROG_CNTR_CLEAR": "Do not clear the program counter", "PROG_CNTR_CLEAR_regRESERVED32 Reserved": 0, "PROG_CNTR_LENGTH0_reg_PROG_LENGTH_MSB": 0, "PROG_CNTR_LENGTH0_regRESERVED33 Reserved": 0, "PROG_CNTR_LENGTH1_reg_PROG_LENGTH_LSB": 0, "PROG_CNTR_MAXLENGTH0_reg_PROG_MAXLENGTH_MSB": 0, "PROG_CNTR_MAXLENGTH0_regRESERVED34 Reserved": 0, "PROG_CNTR_MAXLENGTH1_reg_PROG_MAXLENGTH_LSB": 0, "DMIC_CTRL0_reg_DMIC_EN": "Digital microphone disabled", "DMIC_CTRL0_reg_DMSW": "Normal", "DMIC_CTRL0_reg_DMPOL": "Data polarity normal", "DMIC_CTRL0_reg_HPF": "HPF disabled", "DMIC_CTRL0_reg_DMIC_CLK": "Input BCLK0", "DMIC_CTRL0_regRESERVED36 Reserved": 0, "DMIC_CTRL0_reg_MIC_DATA_SRC": "MP pin 0", "DMIC_CTRL0_reg_CUTOFF": "3.73 Hz", "DMIC_CTRL0_regRESERVED35 Reserved": 0, "DMIC_CTRL1_reg_DMIC_EN": "Digital microphone disabled", "DMIC_CTRL1_reg_DMSW": "Normal", "DMIC_CTRL1_reg_DMPOL": "Data polarity normal", "DMIC_CTRL1_reg_HPF": "HPF disabled", "DMIC_CTRL1_reg_DMIC_CLK": "Input BCLK0", "DMIC_CTRL1_regRESERVED38 Reserved": 0, "DMIC_CTRL1_reg_MIC_DATA_SRC": "MP pin 0", "DMIC_CTRL1_reg_CUTOFF": "3.73 Hz", "DMIC_CTRL1_regRESERVED37 Reserved": 0, "FTDM_IN0_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN0_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN0_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN0_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN0_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN0_regRESERVED39 Reserved": 0, "FTDM_IN1_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN1_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN1_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN1_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN1_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN1_regRESERVED40 Reserved": 0, "FTDM_IN2_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN2_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN2_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN2_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN2_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN2_regRESERVED41 Reserved": 0, "FTDM_IN3_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN3_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN3_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN3_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN3_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN3_regRESERVED42 Reserved": 0, "FTDM_IN4_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN4_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN4_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN4_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN4_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN4_regRESERVED43 Reserved": 0, "FTDM_IN5_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN5_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN5_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN5_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN5_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN5_regRESERVED44 Reserved": 0, "FTDM_IN6_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN6_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN6_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN6_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN6_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN6_regRESERVED45 Reserved": 0, "FTDM_IN7_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN7_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN7_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN7_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN7_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN7_regRESERVED46 Reserved": 0, "FTDM_IN8_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN8_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN8_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN8_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN8_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN8_regRESERVED47 Reserved": 0, "FTDM_IN9_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN9_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN9_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN9_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN9_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN9_regRESERVED48 Reserved": 0, "FTDM_IN10_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN10_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN10_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN10_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN10_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN10_regRESERVED49 Reserved": 0, "FTDM_IN11_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN11_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN11_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN11_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN11_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN11_regRESERVED50 Reserved": 0, "FTDM_IN12_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN12_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN12_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN12_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN12_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN12_regRESERVED51 Reserved": 0, "FTDM_IN13_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN13_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN13_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN13_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN13_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN13_regRESERVED52 Reserved": 0, "FTDM_IN14_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN14_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN14_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN14_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN14_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN14_regRESERVED53 Reserved": 0, "FTDM_IN15_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN15_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN15_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN15_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN15_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN15_regRESERVED54 Reserved": 0, "FTDM_IN16_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN16_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN16_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN16_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN16_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN16_regRESERVED55 Reserved": 0, "FTDM_IN17_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN17_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN17_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN17_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN17_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN17_regRESERVED56 Reserved": 0, "FTDM_IN18_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN18_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN18_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN18_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN18_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN18_regRESERVED57 Reserved": 0, "FTDM_IN19_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN19_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN19_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN19_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN19_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN19_regRESERVED58 Reserved": 0, "FTDM_IN20_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN20_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN20_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN20_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN20_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN20_regRESERVED59 Reserved": 0, "FTDM_IN21_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN21_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN21_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN21_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN21_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN21_regRESERVED60 Reserved": 0, "FTDM_IN22_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN22_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN22_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN22_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN22_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN22_regRESERVED61 Reserved": 0, "FTDM_IN23_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN23_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN23_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN23_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN23_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN23_regRESERVED62 Reserved": 0, "FTDM_IN24_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN24_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN24_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN24_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN24_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN24_regRESERVED63 Reserved": 0, "FTDM_IN25_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN25_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN25_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN25_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN25_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN25_regRESERVED64 Reserved": 0, "FTDM_IN26_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN26_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN26_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN26_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN26_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN26_regRESERVED65 Reserved": 0, "FTDM_IN27_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN27_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN27_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN27_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN27_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN27_regRESERVED66 Reserved": 0, "FTDM_IN28_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN28_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN28_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN28_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN28_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN28_regRESERVED67 Reserved": 0, "FTDM_IN29_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN29_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN29_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN29_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN29_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN29_regRESERVED68 Reserved": 0, "FTDM_IN30_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN30_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN30_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN30_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN30_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN30_regRESERVED69 Reserved": 0, "FTDM_IN31_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN31_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN31_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN31_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN31_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN31_regRESERVED70 Reserved": 0, "FTDM_IN32_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN32_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN32_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN32_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN32_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN32_regRESERVED71 Reserved": 0, "FTDM_IN33_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN33_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN33_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN33_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN33_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN33_regRESERVED72 Reserved": 0, "FTDM_IN34_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN34_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN34_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN34_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN34_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN34_regRESERVED73 Reserved": 0, "FTDM_IN35_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN35_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN35_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN35_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN35_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN35_regRESERVED74 Reserved": 0, "FTDM_IN36_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN36_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN36_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN36_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN36_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN36_regRESERVED75 Reserved": 0, "FTDM_IN37_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN37_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN37_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN37_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN37_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN37_regRESERVED76 Reserved": 0, "FTDM_IN38_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN38_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN38_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN38_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN38_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN38_regRESERVED77 Reserved": 0, "FTDM_IN39_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN39_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN39_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN39_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN39_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN39_regRESERVED78 Reserved": 0, "FTDM_IN40_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN40_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN40_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN40_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN40_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN40_regRESERVED79 Reserved": 0, "FTDM_IN41_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN41_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN41_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN41_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN41_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN41_regRESERVED80 Reserved": 0, "FTDM_IN42_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN42_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN42_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN42_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN42_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN42_regRESERVED81 Reserved": 0, "FTDM_IN43_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN43_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN43_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN43_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN43_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN43_regRESERVED82 Reserved": 0, "FTDM_IN44_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN44_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN44_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN44_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN44_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN44_regRESERVED83 Reserved": 0, "FTDM_IN45_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN45_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN45_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN45_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN45_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN45_regRESERVED84 Reserved": 0, "FTDM_IN46_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN46_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN46_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN46_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN46_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN46_regRESERVED85 Reserved": 0, "FTDM_IN47_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN47_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN47_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN47_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN47_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN47_regRESERVED86 Reserved": 0, "FTDM_IN48_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN48_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN48_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN48_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN48_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN48_regRESERVED87 Reserved": 0, "FTDM_IN49_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN49_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN49_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN49_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN49_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN49_regRESERVED88 Reserved": 0, "FTDM_IN50_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN50_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN50_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN50_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN50_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN50_regRESERVED89 Reserved": 0, "FTDM_IN51_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN51_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN51_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN51_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN51_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN51_regRESERVED90 Reserved": 0, "FTDM_IN52_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN52_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN52_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN52_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN52_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN52_regRESERVED91 Reserved": 0, "FTDM_IN53_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN53_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN53_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN53_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN53_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN53_regRESERVED92 Reserved": 0, "FTDM_IN54_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN54_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN54_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN54_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN54_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN54_regRESERVED93 Reserved": 0, "FTDM_IN55_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN55_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN55_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN55_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN55_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN55_regRESERVED94 Reserved": 0, "FTDM_IN56_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN56_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN56_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN56_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN56_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN56_regRESERVED95 Reserved": 0, "FTDM_IN57_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN57_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN57_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN57_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN57_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN57_regRESERVED96 Reserved": 0, "FTDM_IN58_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN58_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN58_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN58_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN58_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN58_regRESERVED97 Reserved": 0, "FTDM_IN59_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN59_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN59_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN59_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN59_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN59_regRESERVED98 Reserved": 0, "FTDM_IN60_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN60_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN60_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN60_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN60_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN60_regRESERVED99 Reserved": 0, "FTDM_IN61_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN61_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN61_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN61_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN61_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN61_regRESERVED100 Reserved": 0, "FTDM_IN62_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN62_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN62_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN62_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN62_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN62_regRESERVED101 Reserved": 0, "FTDM_IN63_reg_BYTE_IN_POS": "Most significant byte [31:24]", "FTDM_IN63_reg_CHANNEL_IN_POS": "Position 0", "FTDM_IN63_reg_SERIAL_IN_SEL": "FTDM byte comes from SIN2", "FTDM_IN63_reg_REVERSE_IN_BYTE": "Do not reverse bits", "FTDM_IN63_reg_SLOT_ENABLE_IN": "Disable byte", "FTDM_IN63_regRESERVED102 Reserved": 0, "FTDM_OUT0_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT0_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT0_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT0_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT0_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT0_regRESERVED103 Reserved": 0, "FTDM_OUT1_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT1_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT1_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT1_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT1_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT1_regRESERVED104 Reserved": 0, "FTDM_OUT2_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT2_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT2_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT2_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT2_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT2_regRESERVED105 Reserved": 0, "FTDM_OUT3_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT3_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT3_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT3_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT3_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT3_regRESERVED106 Reserved": 0, "FTDM_OUT4_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT4_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT4_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT4_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT4_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT4_regRESERVED107 Reserved": 0, "FTDM_OUT5_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT5_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT5_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT5_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT5_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT5_regRESERVED108 Reserved": 0, "FTDM_OUT6_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT6_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT6_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT6_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT6_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT6_regRESERVED109 Reserved": 0, "FTDM_OUT7_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT7_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT7_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT7_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT7_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT7_regRESERVED110 Reserved": 0, "FTDM_OUT8_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT8_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT8_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT8_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT8_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT8_regRESERVED111 Reserved": 0, "FTDM_OUT9_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT9_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT9_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT9_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT9_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT9_regRESERVED112 Reserved": 0, "FTDM_OUT10_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT10_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT10_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT10_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT10_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT10_regRESERVED113 Reserved": 0, "FTDM_OUT11_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT11_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT11_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT11_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT11_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT11_regRESERVED114 Reserved": 0, "FTDM_OUT12_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT12_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT12_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT12_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT12_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT12_regRESERVED115 Reserved": 0, "FTDM_OUT13_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT13_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT13_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT13_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT13_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT13_regRESERVED116 Reserved": 0, "FTDM_OUT14_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT14_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT14_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT14_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT14_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT14_regRESERVED117 Reserved": 0, "FTDM_OUT15_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT15_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT15_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT15_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT15_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT15_regRESERVED118 Reserved": 0, "FTDM_OUT16_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT16_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT16_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT16_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT16_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT16_regRESERVED119 Reserved": 0, "FTDM_OUT17_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT17_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT17_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT17_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT17_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT17_regRESERVED120 Reserved": 0, "FTDM_OUT18_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT18_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT18_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT18_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT18_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT18_regRESERVED121 Reserved": 0, "FTDM_OUT19_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT19_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT19_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT19_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT19_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT19_regRESERVED122 Reserved": 0, "FTDM_OUT20_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT20_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT20_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT20_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT20_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT20_regRESERVED123 Reserved": 0, "FTDM_OUT21_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT21_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT21_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT21_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT21_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT21_regRESERVED124 Reserved": 0, "FTDM_OUT22_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT22_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT22_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT22_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT22_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT22_regRESERVED125 Reserved": 0, "FTDM_OUT23_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT23_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT23_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT23_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT23_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT23_regRESERVED126 Reserved": 0, "FTDM_OUT24_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT24_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT24_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT24_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT24_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT24_regRESERVED127 Reserved": 0, "FTDM_OUT25_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT25_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT25_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT25_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT25_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT25_regRESERVED128 Reserved": 0, "FTDM_OUT26_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT26_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT26_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT26_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT26_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT26_regRESERVED129 Reserved": 0, "FTDM_OUT27_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT27_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT27_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT27_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT27_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT27_regRESERVED130 Reserved": 0, "FTDM_OUT28_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT28_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT28_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT28_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT28_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT28_regRESERVED131 Reserved": 0, "FTDM_OUT29_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT29_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT29_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT29_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT29_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT29_regRESERVED132 Reserved": 0, "FTDM_OUT30_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT30_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT30_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT30_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT30_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT30_regRESERVED133 Reserved": 0, "FTDM_OUT31_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT31_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT31_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT31_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT31_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT31_regRESERVED134 Reserved": 0, "FTDM_OUT32_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT32_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT32_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT32_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT32_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT32_regRESERVED135 Reserved": 0, "FTDM_OUT33_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT33_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT33_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT33_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT33_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT33_regRESERVED136 Reserved": 0, "FTDM_OUT34_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT34_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT34_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT34_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT34_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT34_regRESERVED137 Reserved": 0, "FTDM_OUT35_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT35_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT35_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT35_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT35_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT35_regRESERVED138 Reserved": 0, "FTDM_OUT36_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT36_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT36_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT36_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT36_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT36_regRESERVED139 Reserved": 0, "FTDM_OUT37_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT37_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT37_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT37_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT37_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT37_regRESERVED140 Reserved": 0, "FTDM_OUT38_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT38_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT38_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT38_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT38_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT38_regRESERVED141 Reserved": 0, "FTDM_OUT39_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT39_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT39_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT39_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT39_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT39_regRESERVED142 Reserved": 0, "FTDM_OUT40_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT40_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT40_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT40_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT40_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT40_regRESERVED143 Reserved": 0, "FTDM_OUT41_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT41_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT41_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT41_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT41_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT41_regRESERVED144 Reserved": 0, "FTDM_OUT42_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT42_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT42_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT42_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT42_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT42_regRESERVED145 Reserved": 0, "FTDM_OUT43_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT43_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT43_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT43_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT43_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT43_regRESERVED146 Reserved": 0, "FTDM_OUT44_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT44_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT44_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT44_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT44_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT44_regRESERVED147 Reserved": 0, "FTDM_OUT45_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT45_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT45_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT45_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT45_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT45_regRESERVED148 Reserved": 0, "FTDM_OUT46_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT46_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT46_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT46_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT46_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT46_regRESERVED149 Reserved": 0, "FTDM_OUT47_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT47_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT47_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT47_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT47_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT47_regRESERVED150 Reserved": 0, "FTDM_OUT48_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT48_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT48_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT48_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT48_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT48_regRESERVED151 Reserved": 0, "FTDM_OUT49_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT49_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT49_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT49_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT49_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT49_regRESERVED152 Reserved": 0, "FTDM_OUT50_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT50_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT50_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT50_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT50_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT50_regRESERVED153 Reserved": 0, "FTDM_OUT51_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT51_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT51_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT51_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT51_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT51_regRESERVED154 Reserved": 0, "FTDM_OUT52_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT52_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT52_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT52_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT52_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT52_regRESERVED155 Reserved": 0, "FTDM_OUT53_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT53_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT53_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT53_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT53_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT53_regRESERVED156 Reserved": 0, "FTDM_OUT54_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT54_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT54_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT54_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT54_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT54_regRESERVED157 Reserved": 0, "FTDM_OUT55_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT55_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT55_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT55_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT55_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT55_regRESERVED158 Reserved": 0, "FTDM_OUT56_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT56_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT56_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT56_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT56_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT56_regRESERVED159 Reserved": 0, "FTDM_OUT57_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT57_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT57_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT57_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT57_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT57_regRESERVED160 Reserved": 0, "FTDM_OUT58_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT58_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT58_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT58_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT58_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT58_regRESERVED161 Reserved": 0, "FTDM_OUT59_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT59_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT59_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT59_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT59_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT59_regRESERVED162 Reserved": 0, "FTDM_OUT60_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT60_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT60_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT60_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT60_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT60_regRESERVED163 Reserved": 0, "FTDM_OUT61_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT61_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT61_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT61_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT61_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT61_regRESERVED164 Reserved": 0, "FTDM_OUT62_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT62_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT62_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT62_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT62_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT62_regRESERVED165 Reserved": 0, "FTDM_OUT63_reg_BYTE_OUT_POS": "Position 0", "FTDM_OUT63_reg_CHANNEL_OUT_POS": "Source channel 0", "FTDM_OUT63_reg_SERIAL_OUT_SEL": "FTDM byte comes from SOUT2", "FTDM_OUT63_reg_REVERSE_OUT_BYTE": "Do not reverse byte", "FTDM_OUT63_reg_SLOT_ENABLE_OUT": "Disable slot", "FTDM_OUT63_regRESERVED166 Reserved": 0, "MP0_MODE_reg_MP_ENABLE": "Primary clock or control port function", "MP0_MODE_reg_MP_MODE": "Input from pin", "MP0_MODE_reg_DEBOUNCE_VALUE": "No debounce", "MP0_MODE_reg_SS_SELECT": "Slave select channel 0", "MP0_MODE_regRESERVED167 Reserved": 0, "MP1_MODE_reg_MP_ENABLE": "Primary clock or control port function", "MP1_MODE_reg_MP_MODE": "Input from pin", "MP1_MODE_reg_DEBOUNCE_VALUE": "No debounce", "MP1_MODE_reg_SS_SELECT": "Slave select channel 0", "MP1_MODE_regRESERVED168 Reserved": 0, "MP2_MODE_reg_MP_ENABLE": "Primary clock or control port function", "MP2_MODE_reg_MP_MODE": "Input from pin", "MP2_MODE_reg_DEBOUNCE_VALUE": "No debounce", "MP2_MODE_reg_SS_SELECT": "Slave select channel 0", "MP2_MODE_regRESERVED169 Reserved": 0, "MP3_MODE_reg_MP_ENABLE": "Primary clock or control port function", "MP3_MODE_reg_MP_MODE": "Input from pin", "MP3_MODE_reg_DEBOUNCE_VALUE": "No debounce", "MP3_MODE_reg_SS_SELECT": "Slave select channel 0", "MP3_MODE_regRESERVED170 Reserved": 0, "MP4_MODE_reg_MP_ENABLE": "Primary clock or control port function", "MP4_MODE_reg_MP_MODE": "Input from pin", "MP4_MODE_reg_DEBOUNCE_VALUE": "No debounce", "MP4_MODE_reg_SS_SELECT": "Slave select channel 0", "MP4_MODE_regRESERVED171 Reserved": 0, "MP5_MODE_reg_MP_ENABLE": "Primary clock or control port function", "MP5_MODE_reg_MP_MODE": "Input from pin", "MP5_MODE_reg_DEBOUNCE_VALUE": "No debounce", "MP5_MODE_reg_SS_SELECT": "Slave select channel 0", "MP5_MODE_regRESERVED172 Reserved": 0, "MP6_MODE_reg_MP_ENABLE": "Primary clock or control port function", "MP6_MODE_reg_MP_MODE": "Input from pin", "MP6_MODE_reg_DEBOUNCE_VALUE": "No debounce", "MP6_MODE_reg_SS_SELECT": "Slave select channel 0", "MP6_MODE_regRESERVED173 Reserved": 0, "MP7_MODE_reg_MP_ENABLE": "Primary clock or control port function", "MP7_MODE_reg_MP_MODE": "Input from pin", "MP7_MODE_reg_DEBOUNCE_VALUE": "No debounce", "MP7_MODE_reg_SS_SELECT": "Slave select channel 0", "MP7_MODE_regRESERVED174 Reserved": 0, "MP8_MODE_reg_MP_ENABLE": "Primary clock or control port function", "MP8_MODE_reg_MP_MODE": "Input from pin", "MP8_MODE_reg_DEBOUNCE_VALUE": "No debounce", "MP8_MODE_reg_SS_SELECT": "Slave select channel 0", "MP8_MODE_regRESERVED175 Reserved": 0, "MP9_MODE_reg_MP_ENABLE": "Primary clock or control port function", "MP9_MODE_reg_MP_MODE": "Input from pin", "MP9_MODE_reg_DEBOUNCE_VALUE": "No debounce", "MP9_MODE_reg_SS_SELECT": "Slave select channel 0", "MP9_MODE_regRESERVED176 Reserved": 0, "MP10_MODE_reg_MP_ENABLE": "Primary clock or control port function", "MP10_MODE_reg_MP_MODE": "Input from pin", "MP10_MODE_reg_DEBOUNCE_VALUE": "No debounce", "MP10_MODE_reg_SS_SELECT": "Slave select channel 0", "MP10_MODE_regRESERVED177 Reserved": 0, "MP11_MODE_reg_MP_ENABLE": "Primary clock or control port function", "MP11_MODE_reg_MP_MODE": "Input from pin", "MP11_MODE_reg_DEBOUNCE_VALUE": "No debounce", "MP11_MODE_reg_SS_SELECT": "Slave select channel 0", "MP11_MODE_regRESERVED178 Reserved": 0, "MP12_MODE_reg_MP_ENABLE": "Primary clock or control port function", "MP12_MODE_reg_MP_MODE": "Input from pin", "MP12_MODE_reg_DEBOUNCE_VALUE": "No debounce", "MP12_MODE_reg_SS_SELECT": "Slave select channel 0", "MP12_MODE_regRESERVED179 Reserved": 0, "MP13_MODE_reg_MP_ENABLE": "Primary clock or control port function", "MP13_MODE_reg_MP_MODE": "Input from pin", "MP13_MODE_reg_DEBOUNCE_VALUE": "No debounce", "MP13_MODE_reg_SS_SELECT": "Slave select channel 0", "MP13_MODE_regRESERVED180 Reserved": 0, "MP0_WRITE_reg_MP_REG_WRITE": "MP pin output off", "MP0_WRITE_regRESERVED181 Reserved": 0, "MP1_WRITE_reg_MP_REG_WRITE": "MP pin output off", "MP1_WRITE_regRESERVED182 Reserved": 0, "MP2_WRITE_reg_MP_REG_WRITE": "MP pin output off", "MP2_WRITE_regRESERVED183 Reserved": 0, "MP3_WRITE_reg_MP_REG_WRITE": "MP pin output off", "MP3_WRITE_regRESERVED184 Reserved": 0, "MP4_WRITE_reg_MP_REG_WRITE": "MP pin output off", "MP4_WRITE_regRESERVED185 Reserved": 0, "MP5_WRITE_reg_MP_REG_WRITE": "MP pin output off", "MP5_WRITE_regRESERVED186 Reserved": 0, "MP6_WRITE_reg_MP_REG_WRITE": "MP pin output off", "MP6_WRITE_regRESERVED187 Reserved": 0, "MP7_WRITE_reg_MP_REG_WRITE": "MP pin output off", "MP7_WRITE_regRESERVED188 Reserved": 0, "MP8_WRITE_reg_MP_REG_WRITE": "MP pin output off", "MP8_WRITE_regRESERVED189 Reserved": 0, "MP9_WRITE_reg_MP_REG_WRITE": "MP pin output off", "MP9_WRITE_regRESERVED190 Reserved": 0, "MP10_WRITE_reg_MP_REG_WRITE": "MP pin output off", "MP10_WRITE_regRESERVED191 Reserved": 0, "MP11_WRITE_reg_MP_REG_WRITE": "MP pin output off", "MP11_WRITE_regRESERVED192 Reserved": 0, "MP12_WRITE_reg_MP_REG_WRITE": "MP pin output off", "MP12_WRITE_regRESERVED193 Reserved": 0, "MP13_WRITE_reg_MP_REG_WRITE": "MP pin output off", "MP13_WRITE_regRESERVED194 Reserved": 0, "MP0_READ_reg_MP_REG_READ": "MP pin input low", "MP0_READ_regRESERVED195 Reserved": 0, "MP1_READ_reg_MP_REG_READ": "MP pin input low", "MP1_READ_regRESERVED196 Reserved": 0, "MP2_READ_reg_MP_REG_READ": "MP pin input low", "MP2_READ_regRESERVED197 Reserved": 0, "MP3_READ_reg_MP_REG_READ": "MP pin input low", "MP3_READ_regRESERVED198 Reserved": 0, "MP4_READ_reg_MP_REG_READ": "MP pin input low", "MP4_READ_regRESERVED199 Reserved": 0, "MP5_READ_reg_MP_REG_READ": "MP pin input low", "MP5_READ_regRESERVED200 Reserved": 0, "MP6_READ_reg_MP_REG_READ": "MP pin input low", "MP6_READ_regRESERVED201 Reserved": 0, "MP7_READ_reg_MP_REG_READ": "MP pin input low", "MP7_READ_regRESERVED202 Reserved": 0, "MP8_READ_reg_MP_REG_READ": "MP pin input low", "MP8_READ_regRESERVED203 Reserved": 0, "MP9_READ_reg_MP_REG_READ": "MP pin input low", "MP9_READ_regRESERVED204 Reserved": 0, "MP10_READ_reg_MP_REG_READ": "MP pin input low", "MP10_READ_regRESERVED205 Reserved": 0, "MP11_READ_reg_MP_REG_READ": "MP pin input low", "MP11_READ_regRESERVED206 Reserved": 0, "MP12_READ_reg_MP_REG_READ": "MP pin input low", "MP12_READ_regRESERVED207 Reserved": 0, "MP13_READ_reg_MP_REG_READ": "MP pin input low", "MP13_READ_regRESERVED208 Reserved": 0, "BCLK_IN0_PIN_reg_BCLK_IN_DRIVE": "Lowest", "BCLK_IN0_PIN_reg_BCLK_IN_SLEW": "Fast", "BCLK_IN0_PIN_reg_BCLK_IN_PULL": "Pull-down enabled", "BCLK_IN0_PIN_regRESERVED209 Reserved": 0, "BCLK_IN1_PIN_reg_BCLK_IN_DRIVE": "Lowest", "BCLK_IN1_PIN_reg_BCLK_IN_SLEW": "Fast", "BCLK_IN1_PIN_reg_BCLK_IN_PULL": "Pull-down enabled", "BCLK_IN1_PIN_regRESERVED210 Reserved": 0, "BCLK_IN2_PIN_reg_BCLK_IN_DRIVE": "Lowest", "BCLK_IN2_PIN_reg_BCLK_IN_SLEW": "Fast", "BCLK_IN2_PIN_reg_BCLK_IN_PULL": "Pull-down enabled", "BCLK_IN2_PIN_regRESERVED211 Reserved": 0, "BCLK_IN3_PIN_reg_BCLK_IN_DRIVE": "Lowest", "BCLK_IN3_PIN_reg_BCLK_IN_SLEW": "Fast", "BCLK_IN3_PIN_reg_BCLK_IN_PULL": "Pull-down enabled", "BCLK_IN3_PIN_regRESERVED212 Reserved": 0, "BCLK_OUT0_PIN_reg_BCLK_OUT_DRIVE": "Lowest", "BCLK_OUT0_PIN_reg_BCLK_OUT_SLEW": "Fast", "BCLK_OUT0_PIN_reg_BCLK_OUT_PULL": "Pull-down enabled", "BCLK_OUT0_PIN_regRESERVED213 Reserved": 0, "BCLK_OUT1_PIN_reg_BCLK_OUT_DRIVE": "Lowest", "BCLK_OUT1_PIN_reg_BCLK_OUT_SLEW": "Fast", "BCLK_OUT1_PIN_reg_BCLK_OUT_PULL": "Pull-down enabled", "BCLK_OUT1_PIN_regRESERVED214 Reserved": 0, "BCLK_OUT2_PIN_reg_BCLK_OUT_DRIVE": "Lowest", "BCLK_OUT2_PIN_reg_BCLK_OUT_SLEW": "Fast", "BCLK_OUT2_PIN_reg_BCLK_OUT_PULL": "Pull-down enabled", "BCLK_OUT2_PIN_regRESERVED215 Reserved": 0, "BCLK_OUT3_PIN_reg_BCLK_OUT_DRIVE": "Lowest", "BCLK_OUT3_PIN_reg_BCLK_OUT_SLEW": "Fast", "BCLK_OUT3_PIN_reg_BCLK_OUT_PULL": "Pull-down enabled", "BCLK_OUT3_PIN_regRESERVED216 Reserved": 0, "LRCLK_IN0_PIN_reg_LRCLK_IN_DRIVE": "Lowest", "LRCLK_IN0_PIN_reg_LRCLK_IN_SLEW": "Fast", "LRCLK_IN0_PIN_reg_LRCLK_IN_PULL": "Pull-down enabled", "LRCLK_IN0_PIN_regRESERVED217 Reserved": 0, "LRCLK_IN1_PIN_reg_LRCLK_IN_DRIVE": "Lowest", "LRCLK_IN1_PIN_reg_LRCLK_IN_SLEW": "Fast", "LRCLK_IN1_PIN_reg_LRCLK_IN_PULL": "Pull-down enabled", "LRCLK_IN1_PIN_regRESERVED218 Reserved": 0, "LRCLK_IN2_PIN_reg_LRCLK_IN_DRIVE": "Lowest", "LRCLK_IN2_PIN_reg_LRCLK_IN_SLEW": "Fast", "LRCLK_IN2_PIN_reg_LRCLK_IN_PULL": "Pull-down enabled", "LRCLK_IN2_PIN_regRESERVED219 Reserved": 0, "LRCLK_IN3_PIN_reg_LRCLK_IN_DRIVE": "Lowest", "LRCLK_IN3_PIN_reg_LRCLK_IN_SLEW": "Fast", "LRCLK_IN3_PIN_reg_LRCLK_IN_PULL": "Pull-down enabled", "LRCLK_IN3_PIN_regRESERVED220 Reserved": 0, "LRCLK_OUT0_PIN_reg_LRCLK_OUT_DRIVE": "Lowest", "LRCLK_OUT0_PIN_reg_LRCLK_OUT_SLEW": "Fast", "LRCLK_OUT0_PIN_reg_LRCLK_OUT_PULL": "Pull-down enabled", "LRCLK_OUT0_PIN_regRESERVED221 Reserved": 0, "LRCLK_OUT1_PIN_reg_LRCLK_OUT_DRIVE": "Lowest", "LRCLK_OUT1_PIN_reg_LRCLK_OUT_SLEW": "Fast", "LRCLK_OUT1_PIN_reg_LRCLK_OUT_PULL": "Pull-down enabled", "LRCLK_OUT1_PIN_regRESERVED222 Reserved": 0, "LRCLK_OUT2_PIN_reg_LRCLK_OUT_DRIVE": "Lowest", "LRCLK_OUT2_PIN_reg_LRCLK_OUT_SLEW": "Fast", "LRCLK_OUT2_PIN_reg_LRCLK_OUT_PULL": "Pull-down enabled", "LRCLK_OUT2_PIN_regRESERVED223 Reserved": 0, "LRCLK_OUT3_PIN_reg_LRCLK_OUT_DRIVE": "Lowest", "LRCLK_OUT3_PIN_reg_LRCLK_OUT_SLEW": "Fast", "LRCLK_OUT3_PIN_reg_LRCLK_OUT_PULL": "Pull-down enabled", "LRCLK_OUT3_PIN_regRESERVED224 Reserved": 0, "SDATA_IN0_PIN_reg_SDATA_IN_DRIVE": "Lowest", "SDATA_IN0_PIN_reg_SDATA_IN_SLEW": "Fast", "SDATA_IN0_PIN_reg_SDATA_IN_PULL": "Pull-down enabled", "SDATA_IN0_PIN_regRESERVED225 Reserved": 0, "SDATA_IN1_PIN_reg_SDATA_IN_DRIVE": "Lowest", "SDATA_IN1_PIN_reg_SDATA_IN_SLEW": "Fast", "SDATA_IN1_PIN_reg_SDATA_IN_PULL": "Pull-down enabled", "SDATA_IN1_PIN_regRESERVED226 Reserved": 0, "SDATA_IN2_PIN_reg_SDATA_IN_DRIVE": "Lowest", "SDATA_IN2_PIN_reg_SDATA_IN_SLEW": "Fast", "SDATA_IN2_PIN_reg_SDATA_IN_PULL": "Pull-down enabled", "SDATA_IN2_PIN_regRESERVED227 Reserved": 0, "SDATA_IN3_PIN_reg_SDATA_IN_DRIVE": "Lowest", "SDATA_IN3_PIN_reg_SDATA_IN_SLEW": "Fast", "SDATA_IN3_PIN_reg_SDATA_IN_PULL": "Pull-down enabled", "SDATA_IN3_PIN_regRESERVED228 Reserved": 0, "SDATA_OUT0_PIN_reg_SDATA_OUT_DRIVE": "Lowest", "SDATA_OUT0_PIN_reg_SDATA_OUT_SLEW": "Fast", "SDATA_OUT0_PIN_reg_SDATA_OUT_PULL": "Pull-down disabled", "SDATA_OUT0_PIN_regRESERVED229 Reserved": 0, "SDATA_OUT1_PIN_reg_SDATA_OUT_DRIVE": "Lowest", "SDATA_OUT1_PIN_reg_SDATA_OUT_SLEW": "Fast", "SDATA_OUT1_PIN_reg_SDATA_OUT_PULL": "Pull-down disabled", "SDATA_OUT1_PIN_regRESERVED230 Reserved": 0, "SDATA_OUT2_PIN_reg_SDATA_OUT_DRIVE": "Lowest", "SDATA_OUT2_PIN_reg_SDATA_OUT_SLEW": "Fast", "SDATA_OUT2_PIN_reg_SDATA_OUT_PULL": "Pull-down disabled", "SDATA_OUT2_PIN_regRESERVED231 Reserved": 0, "SDATA_OUT3_PIN_reg_SDATA_OUT_DRIVE": "Lowest", "SDATA_OUT3_PIN_reg_SDATA_OUT_SLEW": "Fast", "SDATA_OUT3_PIN_reg_SDATA_OUT_PULL": "Pull-down disabled", "SDATA_OUT3_PIN_regRESERVED232 Reserved": 0, "SPDIF_TX_PIN_reg_SPDIF_TX_DRIVE": "Lowest", "SPDIF_TX_PIN_reg_SPDIF_TX_SLEW": "Fast", "SPDIF_TX_PIN_reg_SPDIF_TX_PULL": "Pull-down disabled", "SPDIF_TX_PIN_regRESERVED233 Reserved": 0, "SCLK_SCL_PIN_reg_SCLK_SCL_DRIVE": "Lowest", "SCLK_SCL_PIN_reg_SCLK_SCL_SLEW": "Fast", "SCLK_SCL_PIN_reg_SCLK_SCL_PULL": "Pull-up disabled", "SCLK_SCL_PIN_regRESERVED234 Reserved": 0, "MISO_SDA_PIN_reg_MISO_SDA_DRIVE": "Lowest", "MISO_SDA_PIN_reg_MISO_SDA_SLEW": "Fast", "MISO_SDA_PIN_reg_MISO_SDA_PULL": "Pull-up disabled", "MISO_SDA_PIN_regRESERVED235 Reserved": 0, "SS_PIN_reg_SS_DRIVE": "Lowest", "SS_PIN_reg_SS_SLEW": "Fast", "SS_PIN_reg_SS_PULL": "Pull-up enabled", "SS_PIN_regRESERVED236 Reserved": 0, "MOSI_ADDR1_PIN_reg_MOSI_ADDR1_DRIVE": "Lowest", "MOSI_ADDR1_PIN_reg_MOSI_ADDR1_SLEW": "Fast", "MOSI_ADDR1_PIN_reg_MOSI_ADDR1_PULL": "Pull-up enabled", "MOSI_ADDR1_PIN_regRESERVED237 Reserved": 0, "SCLK_SCL_M_PIN_reg_SCLK_SCL_M_DRIVE": "Lowest", "SCLK_SCL_M_PIN_reg_SCLK_SCL_M_SLEW": "Fast", "SCLK_SCL_M_PIN_reg_SCLK_SCL_M_PULL": "Pull-up disabled", "SCLK_SCL_M_PIN_regRESERVED238 Reserved": 0, "MISO_SDA_M_PIN_reg_MISO_SDA_M_DRIVE": "Lowest", "MISO_SDA_M_PIN_reg_MISO_SDA_M_SLEW": "Fast", "MISO_SDA_M_PIN_reg_MISO_SDA_M_PULL": "Pull-up disabled", "MISO_SDA_M_PIN_regRESERVED239 Reserved": 0, "SS_M_PIN_reg_SS_M_DRIVE": "Lowest", "SS_M_PIN_reg_SS_M_SLEW": "Fast", "SS_M_PIN_reg_SS_M_PULL": "Pull-up enabled", "SS_M_PIN_regRESERVED240 Reserved": 0, "MOSI_M_PIN_reg_MOSI_M_DRIVE": "Lowest", "MOSI_M_PIN_reg_MOSI_M_SLEW": "Fast", "MOSI_M_PIN_reg_MOSI_M_PULL": "Pull-up enabled", "MOSI_M_PIN_regRESERVED241 Reserved": 0, "MP6_PIN_reg_MP6_DRIVE": "Lowest", "MP6_PIN_reg_MP6_SLEW": "Fast", "MP6_PIN_reg_MP6_PULL": "Pull-down enabled", "MP6_PIN_regRESERVED242 Reserved": 0, "MP7_PIN_reg_MP7_DRIVE": "Lowest", "MP7_PIN_reg_MP7_SLEW": "Fast", "MP7_PIN_reg_MP7_PULL": "Pull-down enabled", "MP7_PIN_regRESERVED243 Reserved": 0, "CLKOUT_PIN_reg_CLKOUT_DRIVE": "Lowest", "CLKOUT_PIN_reg_CLKOUT_SLEW": "Fast", "CLKOUT_PIN_reg_CLKOUT_PULL": "Pull-down disabled", "CLKOUT_PIN_regRESERVED244 Reserved": 0, "POWER_ENABLE0_reg_SIN0_PWR": "Enable serial input power", "POWER_ENABLE0_reg_SIN1_PWR": "Enable serial input power", "POWER_ENABLE0_reg_SIN2_PWR": "Enable serial input power", "POWER_ENABLE0_reg_SIN3_PWR": "Enable serial input power", "POWER_ENABLE0_reg_SOUT0_PWR": "Enable serial output power", "POWER_ENABLE0_reg_SOUT1_PWR": "Enable serial output power", "POWER_ENABLE0_reg_SOUT2_PWR": "Enable serial output power", "POWER_ENABLE0_reg_SOUT3_PWR": "Enable serial output power", "POWER_ENABLE0_reg_ASRCBANK0_PWR": "ASRC power enable", "POWER_ENABLE0_reg_ASRCBANK1_PWR": "ASRC power enable", "POWER_ENABLE0_reg_CLK_GEN1_PWR": "Clock generator 1 enabled", "POWER_ENABLE0_reg_CLK_GEN2_PWR": "Clock generator 2 enabled", "POWER_ENABLE0_reg_CLK_GEN3_PWR": "Clock generator 3 enabled", "POWER_ENABLE0_regRESERVED245 Reserved": 0, "POWER_ENABLE1_reg_ADC_PWR": "Enable ADC power", "POWER_ENABLE1_reg_RX_PWR": "Enable S/PDIF receiver power", "POWER_ENABLE1_reg_TX_PWR": "Enable S/PDIF transmitter power", "POWER_ENABLE1_reg_PDM0_PWR": "PDM power enable", "POWER_ENABLE1_reg_PDM1_PWR": "PDM power enable", "POWER_ENABLE1_regRESERVED246 Reserved": 0, "ASRC_INPUT0_reg_ASRC_SOURCE": "Not used", "ASRC_INPUT0_reg_ASRC_SIN_CHANNEL": "Serial input CH0/1", "ASRC_INPUT0_regRESERVED247 Reserved": 0, "ASRC_INPUT1_reg_ASRC_SOURCE": "Not used", "ASRC_INPUT1_reg_ASRC_SIN_CHANNEL": "Serial input CH0/1", "ASRC_INPUT1_regRESERVED248 Reserved": 0, "ASRC_INPUT2_reg_ASRC_SOURCE": "Not used", "ASRC_INPUT2_reg_ASRC_SIN_CHANNEL": "Serial input CH0/1", "ASRC_INPUT2_regRESERVED249 Reserved": 0, "ASRC_INPUT3_reg_ASRC_SOURCE": "Not used", "ASRC_INPUT3_reg_ASRC_SIN_CHANNEL": "Serial input CH0/1", "ASRC_INPUT3_regRESERVED250 Reserved": 0, "ASRC_INPUT4_reg_ASRC_SOURCE": "Not used", "ASRC_INPUT4_reg_ASRC_SIN_CHANNEL": "Serial input CH0/1", "ASRC_INPUT4_regRESERVED251 Reserved": 0, "ASRC_INPUT5_reg_ASRC_SOURCE": "Not used", "ASRC_INPUT5_reg_ASRC_SIN_CHANNEL": "Serial input CH0/1", "ASRC_INPUT5_regRESERVED252 Reserved": 0, "ASRC_INPUT6_reg_ASRC_SOURCE": "Not used", "ASRC_INPUT6_reg_ASRC_SIN_CHANNEL": "Serial input CH0/1", "ASRC_INPUT6_regRESERVED253 Reserved": 0, "ASRC_INPUT7_reg_ASRC_SOURCE": "Not used", "ASRC_INPUT7_reg_ASRC_SIN_CHANNEL": "Serial input CH0/1", "ASRC_INPUT7_regRESERVED254 Reserved": 0, "ASRC_OUT_RATE0_reg_ASRC_RATE": "Off", "ASRC_OUT_RATE0_regRESERVED255 Reserved": 0, "ASRC_OUT_RATE1_reg_ASRC_RATE": "Off", "ASRC_OUT_RATE1_regRESERVED256 Reserved": 0, "ASRC_OUT_RATE2_reg_ASRC_RATE": "Off", "ASRC_OUT_RATE2_regRESERVED257 Reserved": 0, "ASRC_OUT_RATE3_reg_ASRC_RATE": "Off", "ASRC_OUT_RATE3_regRESERVED258 Reserved": 0, "ASRC_OUT_RATE4_reg_ASRC_RATE": "Off", "ASRC_OUT_RATE4_regRESERVED259 Reserved": 0, "ASRC_OUT_RATE5_reg_ASRC_RATE": "Off", "ASRC_OUT_RATE5_regRESERVED260 Reserved": 0, "ASRC_OUT_RATE6_reg_ASRC_RATE": "Off", "ASRC_OUT_RATE6_regRESERVED261 Reserved": 0, "ASRC_OUT_RATE7_reg_ASRC_RATE": "Off", "ASRC_OUT_RATE7_regRESERVED262 Reserved": 0, "SOUT_SOURCE0_reg_SOUT_SOURCE": "From corresponding DSP core output channels", "SOUT_SOURCE0_reg_SOUT_ASRC_SELECT": "ASRC 0", "SOUT_SOURCE0_regRESERVED263 Reserved": 0, "SOUT_SOURCE1_reg_SOUT_SOURCE": "From corresponding DSP core output channels", "SOUT_SOURCE1_reg_SOUT_ASRC_SELECT": "ASRC 0", "SOUT_SOURCE1_regRESERVED264 Reserved": 0, "SOUT_SOURCE2_reg_SOUT_SOURCE": "From corresponding DSP core output channels", "SOUT_SOURCE2_reg_SOUT_ASRC_SELECT": "ASRC 0", "SOUT_SOURCE2_regRESERVED265 Reserved": 0, "SOUT_SOURCE3_reg_SOUT_SOURCE": "From corresponding DSP core output channels", "SOUT_SOURCE3_reg_SOUT_ASRC_SELECT": "ASRC 0", "SOUT_SOURCE3_regRESERVED266 Reserved": 0, "SOUT_SOURCE4_reg_SOUT_SOURCE": "From corresponding DSP core output channels", "SOUT_SOURCE4_reg_SOUT_ASRC_SELECT": "ASRC 0", "SOUT_SOURCE4_regRESERVED267 Reserved": 0, "SOUT_SOURCE5_reg_SOUT_SOURCE": "From corresponding DSP core output channels", "SOUT_SOURCE5_reg_SOUT_ASRC_SELECT": "ASRC 0", "SOUT_SOURCE5_regRESERVED268 Reserved": 0, "SOUT_SOURCE6_reg_SOUT_SOURCE": "From corresponding DSP core output channels", "SOUT_SOURCE6_reg_SOUT_ASRC_SELECT": "ASRC 0", "SOUT_SOURCE6_regRESERVED269 Reserved": 0, "SOUT_SOURCE7_reg_SOUT_SOURCE": "From corresponding DSP core output channels", "SOUT_SOURCE7_reg_SOUT_ASRC_SELECT": "ASRC 0", "SOUT_SOURCE7_regRESERVED270 Reserved": 0, "SOUT_SOURCE8_reg_SOUT_SOURCE": "From corresponding DSP core output channels", "SOUT_SOURCE8_reg_SOUT_ASRC_SELECT": "ASRC 0", "SOUT_SOURCE8_regRESERVED271 Reserved": 0, "SOUT_SOURCE9_reg_SOUT_SOURCE": "From corresponding DSP core output channels", "SOUT_SOURCE9_reg_SOUT_ASRC_SELECT": "ASRC 0", "SOUT_SOURCE9_regRESERVED272 Reserved": 0, "SOUT_SOURCE10_reg_SOUT_SOURCE": "From corresponding DSP core output channels", "SOUT_SOURCE10_reg_SOUT_ASRC_SELECT": "ASRC 0", "SOUT_SOURCE10_regRESERVED273 Reserved": 0, "SOUT_SOURCE11_reg_SOUT_SOURCE": "From corresponding DSP core output channels", "SOUT_SOURCE11_reg_SOUT_ASRC_SELECT": "ASRC 0", "SOUT_SOURCE11_regRESERVED274 Reserved": 0, "SOUT_SOURCE12_reg_SOUT_SOURCE": "From corresponding DSP core output channels", "SOUT_SOURCE12_reg_SOUT_ASRC_SELECT": "ASRC 0", "SOUT_SOURCE12_regRESERVED275 Reserved": 0, "SOUT_SOURCE13_reg_SOUT_SOURCE": "From corresponding DSP core output channels", "SOUT_SOURCE13_reg_SOUT_ASRC_SELECT": "ASRC 0", "SOUT_SOURCE13_regRESERVED276 Reserved": 0, "SOUT_SOURCE14_reg_SOUT_SOURCE": "From corresponding DSP core output channels", "SOUT_SOURCE14_reg_SOUT_ASRC_SELECT": "ASRC 0", "SOUT_SOURCE14_regRESERVED277 Reserved": 0, "SOUT_SOURCE15_reg_SOUT_SOURCE": "From corresponding DSP core output channels", "SOUT_SOURCE15_reg_SOUT_ASRC_SELECT": "ASRC 0", "SOUT_SOURCE15_regRESERVED278 Reserved": 0, "SOUT_SOURCE16_reg_SOUT_SOURCE": "From corresponding DSP core output channels", "SOUT_SOURCE16_reg_SOUT_ASRC_SELECT": "ASRC 0", "SOUT_SOURCE16_regRESERVED279 Reserved": 0, "SOUT_SOURCE17_reg_SOUT_SOURCE": "From corresponding DSP core output channels", "SOUT_SOURCE17_reg_SOUT_ASRC_SELECT": "ASRC 0", "SOUT_SOURCE17_regRESERVED280 Reserved": 0, "SOUT_SOURCE18_reg_SOUT_SOURCE": "From corresponding DSP core output channels", "SOUT_SOURCE18_reg_SOUT_ASRC_SELECT": "ASRC 0", "SOUT_SOURCE18_regRESERVED281 Reserved": 0, "SOUT_SOURCE19_reg_SOUT_SOURCE": "From corresponding DSP core output channels", "SOUT_SOURCE19_reg_SOUT_ASRC_SELECT": "ASRC 0", "SOUT_SOURCE19_regRESERVED282 Reserved": 0, "SOUT_SOURCE20_reg_SOUT_SOURCE": "From corresponding DSP core output channels", "SOUT_SOURCE20_reg_SOUT_ASRC_SELECT": "ASRC 0", "SOUT_SOURCE20_regRESERVED283 Reserved": 0, "SOUT_SOURCE21_reg_SOUT_SOURCE": "From corresponding DSP core output channels", "SOUT_SOURCE21_reg_SOUT_ASRC_SELECT": "ASRC 0", "SOUT_SOURCE21_regRESERVED284 Reserved": 0, "SOUT_SOURCE22_reg_SOUT_SOURCE": "From corresponding DSP core output channels", "SOUT_SOURCE22_reg_SOUT_ASRC_SELECT": "ASRC 0", "SOUT_SOURCE22_regRESERVED285 Reserved": 0, "SOUT_SOURCE23_reg_SOUT_SOURCE": "From corresponding DSP core output channels", "SOUT_SOURCE23_reg_SOUT_ASRC_SELECT": "ASRC 0", "SOUT_SOURCE23_regRESERVED286 Reserved": 0, "SPDIFTX_INPUT_reg_SPDIFTX_SOURCE": "SPDIF Transmitter Disabled", "SPDIFTX_INPUT_regRESERVED287 Reserved": 0, "SERIAL_BYTE_0_0_reg_TDM_MODE": "2 channels, 32 bit/channel", "SERIAL_BYTE_0_0_reg_DATA_FMT": "I2S - BCLK delay by 1", "SERIAL_BYTE_0_0_reg_WORD_LEN": "24 bits", "SERIAL_BYTE_0_0_reg_BCLK_POL": "Negative polarity", "SERIAL_BYTE_0_0_reg_LRCLK_POL": "Negative polarity", "SERIAL_BYTE_0_0_reg_LRCLK_MODE": "50/50 duty cycle clock", "SERIAL_BYTE_0_0_reg_BCLK_SRC": "BCLK is master", "SERIAL_BYTE_0_0_reg_LRCLK_SRC": "LRCLK is master", "SERIAL_BYTE_0_1_reg_FS": "Fs", "SERIAL_BYTE_0_1_reg_CLK_DOMAIN": "Clock generator 1 (48 kHz (FS) generator)", "SERIAL_BYTE_0_1_reg_TRISTATE": "Drive every output channel", "SERIAL_BYTE_0_1_regRESERVED288 Reserved": 0, "SERIAL_BYTE_1_0_reg_TDM_MODE": "2 channels, 32 bit/channel", "SERIAL_BYTE_1_0_reg_DATA_FMT": "I2S - BCLK delay by 1", "SERIAL_BYTE_1_0_reg_WORD_LEN": "24 bits", "SERIAL_BYTE_1_0_reg_BCLK_POL": "Negative polarity", "SERIAL_BYTE_1_0_reg_LRCLK_POL": "Negative polarity", "SERIAL_BYTE_1_0_reg_LRCLK_MODE": "50/50 duty cycle clock", "SERIAL_BYTE_1_0_reg_BCLK_SRC": "BCLK is master", "SERIAL_BYTE_1_0_reg_LRCLK_SRC": "LRCLK is master", "SERIAL_BYTE_1_1_reg_FS": "Fs", "SERIAL_BYTE_1_1_reg_CLK_DOMAIN": "Clock generator 1 (48 kHz (FS) generator)", "SERIAL_BYTE_1_1_reg_TRISTATE": "Drive every output channel", "SERIAL_BYTE_1_1_regRESERVED289 Reserved": 0, "SERIAL_BYTE_2_0_reg_TDM_MODE": "2 channels, 32 bit/channel", "SERIAL_BYTE_2_0_reg_DATA_FMT": "I2S - BCLK delay by 1", "SERIAL_BYTE_2_0_reg_WORD_LEN": "24 bits", "SERIAL_BYTE_2_0_reg_BCLK_POL": "Negative polarity", "SERIAL_BYTE_2_0_reg_LRCLK_POL": "Negative polarity", "SERIAL_BYTE_2_0_reg_LRCLK_MODE": "50/50 duty cycle clock", "SERIAL_BYTE_2_0_reg_BCLK_SRC": "BCLK is master", "SERIAL_BYTE_2_0_reg_LRCLK_SRC": "LRCLK is master", "SERIAL_BYTE_2_1_reg_FS": "Fs", "SERIAL_BYTE_2_1_reg_CLK_DOMAIN": "Clock generator 1 (48 kHz (FS) generator)", "SERIAL_BYTE_2_1_reg_TRISTATE": "Drive every output channel", "SERIAL_BYTE_2_1_regRESERVED290 Reserved": 0, "SERIAL_BYTE_3_0_reg_TDM_MODE": "2 channels, 32 bit/channel", "SERIAL_BYTE_3_0_reg_DATA_FMT": "I2S - BCLK delay by 1", "SERIAL_BYTE_3_0_reg_WORD_LEN": "24 bits", "SERIAL_BYTE_3_0_reg_BCLK_POL": "Negative polarity", "SERIAL_BYTE_3_0_reg_LRCLK_POL": "Negative polarity", "SERIAL_BYTE_3_0_reg_LRCLK_MODE": "50/50 duty cycle clock", "SERIAL_BYTE_3_0_reg_BCLK_SRC": "BCLK is master", "SERIAL_BYTE_3_0_reg_LRCLK_SRC": "LRCLK is master", "SERIAL_BYTE_3_1_reg_FS": "Fs", "SERIAL_BYTE_3_1_reg_CLK_DOMAIN": "Clock generator 1 (48 kHz (FS) generator)", "SERIAL_BYTE_3_1_reg_TRISTATE": "Drive every output channel", "SERIAL_BYTE_3_1_regRESERVED291 Reserved": 0, "SERIAL_BYTE_4_0_reg_TDM_MODE": "2 channels, 32 bit/channel", "SERIAL_BYTE_4_0_reg_DATA_FMT": "I2S - BCLK delay by 1", "SERIAL_BYTE_4_0_reg_WORD_LEN": "24 bits", "SERIAL_BYTE_4_0_reg_BCLK_POL": "Negative polarity", "SERIAL_BYTE_4_0_reg_LRCLK_POL": "Negative polarity", "SERIAL_BYTE_4_0_reg_LRCLK_MODE": "50/50 duty cycle clock", "SERIAL_BYTE_4_0_reg_BCLK_SRC": "BCLK is master", "SERIAL_BYTE_4_0_reg_LRCLK_SRC": "LRCLK is master", "SERIAL_BYTE_4_1_reg_FS": "Fs", "SERIAL_BYTE_4_1_reg_CLK_DOMAIN": "Clock generator 1 (48 kHz (FS) generator)", "SERIAL_BYTE_4_1_reg_TRISTATE": "Drive every output channel", "SERIAL_BYTE_4_1_regRESERVED292 Reserved": 0, "SERIAL_BYTE_5_0_reg_TDM_MODE": "2 channels, 32 bit/channel", "SERIAL_BYTE_5_0_reg_DATA_FMT": "I2S - BCLK delay by 1", "SERIAL_BYTE_5_0_reg_WORD_LEN": "24 bits", "SERIAL_BYTE_5_0_reg_BCLK_POL": "Negative polarity", "SERIAL_BYTE_5_0_reg_LRCLK_POL": "Negative polarity", "SERIAL_BYTE_5_0_reg_LRCLK_MODE": "50/50 duty cycle clock", "SERIAL_BYTE_5_0_reg_BCLK_SRC": "BCLK is master", "SERIAL_BYTE_5_0_reg_LRCLK_SRC": "LRCLK is master", "SERIAL_BYTE_5_1_reg_FS": "Fs", "SERIAL_BYTE_5_1_reg_CLK_DOMAIN": "Clock generator 1 (48 kHz (FS) generator)", "SERIAL_BYTE_5_1_reg_TRISTATE": "Drive every output channel", "SERIAL_BYTE_5_1_regRESERVED293 Reserved": 0, "SERIAL_BYTE_6_0_reg_TDM_MODE": "2 channels, 32 bit/channel", "SERIAL_BYTE_6_0_reg_DATA_FMT": "I2S - BCLK delay by 1", "SERIAL_BYTE_6_0_reg_WORD_LEN": "24 bits", "SERIAL_BYTE_6_0_reg_BCLK_POL": "Negative polarity", "SERIAL_BYTE_6_0_reg_LRCLK_POL": "Negative polarity", "SERIAL_BYTE_6_0_reg_LRCLK_MODE": "50/50 duty cycle clock", "SERIAL_BYTE_6_0_reg_BCLK_SRC": "BCLK is master", "SERIAL_BYTE_6_0_reg_LRCLK_SRC": "LRCLK is master", "SERIAL_BYTE_6_1_reg_FS": "Fs", "SERIAL_BYTE_6_1_reg_CLK_DOMAIN": "Clock generator 1 (48 kHz (FS) generator)", "SERIAL_BYTE_6_1_reg_TRISTATE": "Drive every output channel", "SERIAL_BYTE_6_1_regRESERVED294 Reserved": 0, "SERIAL_BYTE_7_0_reg_TDM_MODE": "2 channels, 32 bit/channel", "SERIAL_BYTE_7_0_reg_DATA_FMT": "I2S - BCLK delay by 1", "SERIAL_BYTE_7_0_reg_WORD_LEN": "24 bits", "SERIAL_BYTE_7_0_reg_BCLK_POL": "Negative polarity", "SERIAL_BYTE_7_0_reg_LRCLK_POL": "Negative polarity", "SERIAL_BYTE_7_0_reg_LRCLK_MODE": "50/50 duty cycle clock", "SERIAL_BYTE_7_0_reg_BCLK_SRC": "BCLK is master", "SERIAL_BYTE_7_0_reg_LRCLK_SRC": "LRCLK is master", "SERIAL_BYTE_7_1_reg_FS": "Fs", "SERIAL_BYTE_7_1_reg_CLK_DOMAIN": "Clock generator 1 (48 kHz (FS) generator)", "SERIAL_BYTE_7_1_reg_TRISTATE": "Drive every output channel", "SERIAL_BYTE_7_1_regRESERVED295 Reserved": 0, "SPDIF_LOCK_DET_reg_LOCK": "No valid input stream", "SPDIF_LOCK_DET_regRESERVED296 Reserved": 0, "SPDIF_RX_CTRL_reg_RX_LENGTHCTRL": "24 bits", "SPDIF_RX_CTRL_reg_FSOUTSTRENGTH": "Strong", "SPDIF_RX_CTRL_reg_FASTLOCK": "Normal", "SPDIF_RX_CTRL_regRESERVED297 Reserved": 0, "SPDIF_RX_DECODE_reg_AUDIO_TYPE": "PCM", "SPDIF_RX_DECODE_reg_COMPR_TYPE": "AC3", "SPDIF_RX_DECODE_reg_RX_WORDLENGTH_L": "Length 16", "SPDIF_RX_DECODE_reg_RX_WORDLENGTH_R": "Length 16", "SPDIF_RX_DECODE_regRESERVED298 Reserved": 0, "SPDIF_RX_COMPRMODE_reg_COMPR_MODE": 0, "SPDIF_RESTART_reg_RESTART_AUDIO": "Does not restart the audio once a re-lock has occurred", "SPDIF_RESTART_regRESERVED299 Reserved": 0, "SPDIF_LOSS_OF_LOCK_reg_LOSS_OF_LOCK": "S/PDIF receiver is locked", "SPDIF_LOSS_OF_LOCK_regRESERVED300 Reserved": 0, "SPDIF_AUX_EN_reg_TDMOUT": "No S/PDIF TDM output", "SPDIF_AUX_EN_reg_TDMOUT_CLK": "Use S/PDIF internally derived S/PDIF BCLK/LRCLK", "SPDIF_AUX_EN_regRESERVED301 Reserved": 0, "SPDIF_RX_AUXBIT_READY_reg_AUXBITS_READY": "Auxiliary bits are not ready", "SPDIF_RX_AUXBIT_READY_regRESERVED302 Reserved": 0, "SPDIF_TX_EN_reg_TXEN": "Disabled", "SPDIF_TX_EN_regRESERVED303 Reserved": 0, "SPDIF_TX_CTRL_reg_TX_LENGTHCTRL": "24 bits", "SPDIF_TX_CTRL_regRESERVED304 Reserved": 0, "SPDIF_TX_AUXBIT_SOURCE_reg_TX_AUXBITS_SOURCE": "Source from register map", "SPDIF_TX_AUXBIT_SOURCE_regRESERVED305 Reserved": 0, "SPDIF_RX_CS_LEFT_0_reg_SPDIF_RX_CS_LEFT": 0, "SPDIF_RX_CS_LEFT_1_reg_SPDIF_RX_CS_LEFT": 0, "SPDIF_RX_CS_LEFT_2_reg_SPDIF_RX_CS_LEFT": 0, "SPDIF_RX_CS_LEFT_3_reg_SPDIF_RX_CS_LEFT": 0, "SPDIF_RX_CS_LEFT_4_reg_SPDIF_RX_CS_LEFT": 0, "SPDIF_RX_CS_LEFT_5_reg_SPDIF_RX_CS_LEFT": 0, "SPDIF_RX_CS_LEFT_6_reg_SPDIF_RX_CS_LEFT": 0, "SPDIF_RX_CS_LEFT_7_reg_SPDIF_RX_CS_LEFT": 0, "SPDIF_RX_CS_LEFT_8_reg_SPDIF_RX_CS_LEFT": 0, "SPDIF_RX_CS_LEFT_9_reg_SPDIF_RX_CS_LEFT": 0, "SPDIF_RX_CS_LEFT_10_reg_SPDIF_RX_CS_LEFT": 0, "SPDIF_RX_CS_LEFT_11_reg_SPDIF_RX_CS_LEFT": 0, "SPDIF_RX_CS_RIGHT_0_reg_SPDIF_RX_CS_RIGHT": 0, "SPDIF_RX_CS_RIGHT_1_reg_SPDIF_RX_CS_RIGHT": 0, "SPDIF_RX_CS_RIGHT_2_reg_SPDIF_RX_CS_RIGHT": 0, "SPDIF_RX_CS_RIGHT_3_reg_SPDIF_RX_CS_RIGHT": 0, "SPDIF_RX_CS_RIGHT_4_reg_SPDIF_RX_CS_RIGHT": 0, "SPDIF_RX_CS_RIGHT_5_reg_SPDIF_RX_CS_RIGHT": 0, "SPDIF_RX_CS_RIGHT_6_reg_SPDIF_RX_CS_RIGHT": 0, "SPDIF_RX_CS_RIGHT_7_reg_SPDIF_RX_CS_RIGHT": 0, "SPDIF_RX_CS_RIGHT_8_reg_SPDIF_RX_CS_RIGHT": 0, "SPDIF_RX_CS_RIGHT_9_reg_SPDIF_RX_CS_RIGHT": 0, "SPDIF_RX_CS_RIGHT_10_reg_SPDIF_RX_CS_RIGHT": 0, "SPDIF_RX_CS_RIGHT_11_reg_SPDIF_RX_CS_RIGHT": 0, "SPDIF_RX_PB_LEFT_0_reg_SPDIF_RX_PB_LEFT": 0, "SPDIF_RX_PB_LEFT_1_reg_SPDIF_RX_PB_LEFT": 0, "SPDIF_RX_PB_LEFT_2_reg_SPDIF_RX_PB_LEFT": 0, "SPDIF_RX_PB_LEFT_3_reg_SPDIF_RX_PB_LEFT": 0, "SPDIF_RX_PB_LEFT_4_reg_SPDIF_RX_PB_LEFT": 0, "SPDIF_RX_PB_LEFT_5_reg_SPDIF_RX_PB_LEFT": 0, "SPDIF_RX_PB_LEFT_6_reg_SPDIF_RX_PB_LEFT": 0, "SPDIF_RX_PB_LEFT_7_reg_SPDIF_RX_PB_LEFT": 0, "SPDIF_RX_PB_LEFT_8_reg_SPDIF_RX_PB_LEFT": 0, "SPDIF_RX_PB_LEFT_9_reg_SPDIF_RX_PB_LEFT": 0, "SPDIF_RX_PB_LEFT_10_reg_SPDIF_RX_PB_LEFT": 0, "SPDIF_RX_PB_LEFT_11_reg_SPDIF_RX_PB_LEFT": 0, "SPDIF_RX_PB_RIGHT_0_reg_SPDIF_RX_PB_RIGHT": 0, "SPDIF_RX_PB_RIGHT_1_reg_SPDIF_RX_PB_RIGHT": 0, "SPDIF_RX_PB_RIGHT_2_reg_SPDIF_RX_PB_RIGHT": 0, "SPDIF_RX_PB_RIGHT_3_reg_SPDIF_RX_PB_RIGHT": 0, "SPDIF_RX_PB_RIGHT_4_reg_SPDIF_RX_PB_RIGHT": 0, "SPDIF_RX_PB_RIGHT_5_reg_SPDIF_RX_PB_RIGHT": 0, "SPDIF_RX_PB_RIGHT_6_reg_SPDIF_RX_PB_RIGHT": 0, "SPDIF_RX_PB_RIGHT_7_reg_SPDIF_RX_PB_RIGHT": 0, "SPDIF_RX_PB_RIGHT_8_reg_SPDIF_RX_PB_RIGHT": 0, "SPDIF_RX_PB_RIGHT_9_reg_SPDIF_RX_PB_RIGHT": 0, "SPDIF_RX_PB_RIGHT_10_reg_SPDIF_RX_PB_RIGHT": 0, "SPDIF_RX_PB_RIGHT_11_reg_SPDIF_RX_PB_RIGHT": 0, "SPDIF_RX_UD_LEFT_0_reg_SPDIF_RX_UD_LEFT": 0, "SPDIF_RX_UD_LEFT_1_reg_SPDIF_RX_UD_LEFT": 0, "SPDIF_RX_UD_LEFT_2_reg_SPDIF_RX_UD_LEFT": 0, "SPDIF_RX_UD_LEFT_3_reg_SPDIF_RX_UD_LEFT": 0, "SPDIF_RX_UD_LEFT_4_reg_SPDIF_RX_UD_LEFT": 0, "SPDIF_RX_UD_LEFT_5_reg_SPDIF_RX_UD_LEFT": 0, "SPDIF_RX_UD_LEFT_6_reg_SPDIF_RX_UD_LEFT": 0, "SPDIF_RX_UD_LEFT_7_reg_SPDIF_RX_UD_LEFT": 0, "SPDIF_RX_UD_LEFT_8_reg_SPDIF_RX_UD_LEFT": 0, "SPDIF_RX_UD_LEFT_9_reg_SPDIF_RX_UD_LEFT": 0, "SPDIF_RX_UD_LEFT_10_reg_SPDIF_RX_UD_LEFT": 0, "SPDIF_RX_UD_LEFT_11_reg_SPDIF_RX_UD_LEFT": 0, "SPDIF_RX_UD_RIGHT_0_reg_SPDIF_RX_UD_RIGHT": 0, "SPDIF_RX_UD_RIGHT_1_reg_SPDIF_RX_UD_RIGHT": 0, "SPDIF_RX_UD_RIGHT_2_reg_SPDIF_RX_UD_RIGHT": 0, "SPDIF_RX_UD_RIGHT_3_reg_SPDIF_RX_UD_RIGHT": 0, "SPDIF_RX_UD_RIGHT_4_reg_SPDIF_RX_UD_RIGHT": 0, "SPDIF_RX_UD_RIGHT_5_reg_SPDIF_RX_UD_RIGHT": 0, "SPDIF_RX_UD_RIGHT_6_reg_SPDIF_RX_UD_RIGHT": 0, "SPDIF_RX_UD_RIGHT_7_reg_SPDIF_RX_UD_RIGHT": 0, "SPDIF_RX_UD_RIGHT_8_reg_SPDIF_RX_UD_RIGHT": 0, "SPDIF_RX_UD_RIGHT_9_reg_SPDIF_RX_UD_RIGHT": 0, "SPDIF_RX_UD_RIGHT_10_reg_SPDIF_RX_UD_RIGHT": 0, "SPDIF_RX_UD_RIGHT_11_reg_SPDIF_RX_UD_RIGHT": 0, "SPDIF_RX_VB_LEFT_0_reg_SPDIF_RX_VB_LEFT": 0, "SPDIF_RX_VB_LEFT_1_reg_SPDIF_RX_VB_LEFT": 0, "SPDIF_RX_VB_LEFT_2_reg_SPDIF_RX_VB_LEFT": 0, "SPDIF_RX_VB_LEFT_3_reg_SPDIF_RX_VB_LEFT": 0, "SPDIF_RX_VB_LEFT_4_reg_SPDIF_RX_VB_LEFT": 0, "SPDIF_RX_VB_LEFT_5_reg_SPDIF_RX_VB_LEFT": 0, "SPDIF_RX_VB_LEFT_6_reg_SPDIF_RX_VB_LEFT": 0, "SPDIF_RX_VB_LEFT_7_reg_SPDIF_RX_VB_LEFT": 0, "SPDIF_RX_VB_LEFT_8_reg_SPDIF_RX_VB_LEFT": 0, "SPDIF_RX_VB_LEFT_9_reg_SPDIF_RX_VB_LEFT": 0, "SPDIF_RX_VB_LEFT_10_reg_SPDIF_RX_VB_LEFT": 0, "SPDIF_RX_VB_LEFT_11_reg_SPDIF_RX_VB_LEFT": 0, "SPDIF_RX_VB_RIGHT_0_reg_SPDIF_RX_VB_RIGHT": 0, "SPDIF_RX_VB_RIGHT_1_reg_SPDIF_RX_VB_RIGHT": 0, "SPDIF_RX_VB_RIGHT_2_reg_SPDIF_RX_VB_RIGHT": 0, "SPDIF_RX_VB_RIGHT_3_reg_SPDIF_RX_VB_RIGHT": 0, "SPDIF_RX_VB_RIGHT_4_reg_SPDIF_RX_VB_RIGHT": 0, "SPDIF_RX_VB_RIGHT_5_reg_SPDIF_RX_VB_RIGHT": 0, "SPDIF_RX_VB_RIGHT_6_reg_SPDIF_RX_VB_RIGHT": 0, "SPDIF_RX_VB_RIGHT_7_reg_SPDIF_RX_VB_RIGHT": 0, "SPDIF_RX_VB_RIGHT_8_reg_SPDIF_RX_VB_RIGHT": 0, "SPDIF_RX_VB_RIGHT_9_reg_SPDIF_RX_VB_RIGHT": 0, "SPDIF_RX_VB_RIGHT_10_reg_SPDIF_RX_VB_RIGHT": 0, "SPDIF_RX_VB_RIGHT_11_reg_SPDIF_RX_VB_RIGHT": 0, "SPDIF_TX_CS_LEFT_0_reg_SPDIF_TX_CS_LEFT": 0, "SPDIF_TX_CS_LEFT_1_reg_SPDIF_TX_CS_LEFT": 0, "SPDIF_TX_CS_LEFT_2_reg_SPDIF_TX_CS_LEFT": 0, "SPDIF_TX_CS_LEFT_3_reg_SPDIF_TX_CS_LEFT": 0, "SPDIF_TX_CS_LEFT_4_reg_SPDIF_TX_CS_LEFT": 0, "SPDIF_TX_CS_LEFT_5_reg_SPDIF_TX_CS_LEFT": 0, "SPDIF_TX_CS_LEFT_6_reg_SPDIF_TX_CS_LEFT": 0, "SPDIF_TX_CS_LEFT_7_reg_SPDIF_TX_CS_LEFT": 0, "SPDIF_TX_CS_LEFT_8_reg_SPDIF_TX_CS_LEFT": 0, "SPDIF_TX_CS_LEFT_9_reg_SPDIF_TX_CS_LEFT": 0, "SPDIF_TX_CS_LEFT_10_reg_SPDIF_TX_CS_LEFT": 0, "SPDIF_TX_CS_LEFT_11_reg_SPDIF_TX_CS_LEFT": 0, "SPDIF_TX_CS_RIGHT_0_reg_SPDIF_TX_CS_RIGHT": 0, "SPDIF_TX_CS_RIGHT_1_reg_SPDIF_TX_CS_RIGHT": 0, "SPDIF_TX_CS_RIGHT_2_reg_SPDIF_TX_CS_RIGHT": 0, "SPDIF_TX_CS_RIGHT_3_reg_SPDIF_TX_CS_RIGHT": 0, "SPDIF_TX_CS_RIGHT_4_reg_SPDIF_TX_CS_RIGHT": 0, "SPDIF_TX_CS_RIGHT_5_reg_SPDIF_TX_CS_RIGHT": 0, "SPDIF_TX_CS_RIGHT_6_reg_SPDIF_TX_CS_RIGHT": 0, "SPDIF_TX_CS_RIGHT_7_reg_SPDIF_TX_CS_RIGHT": 0, "SPDIF_TX_CS_RIGHT_8_reg_SPDIF_TX_CS_RIGHT": 0, "SPDIF_TX_CS_RIGHT_9_reg_SPDIF_TX_CS_RIGHT": 0, "SPDIF_TX_CS_RIGHT_10_reg_SPDIF_TX_CS_RIGHT": 0, "SPDIF_TX_CS_RIGHT_11_reg_SPDIF_TX_CS_RIGHT": 0, "SPDIF_TX_PB_LEFT_0_reg_SPDIF_TX_PB_LEFT": 0, "SPDIF_TX_PB_LEFT_1_reg_SPDIF_TX_PB_LEFT": 0, "SPDIF_TX_PB_LEFT_2_reg_SPDIF_TX_PB_LEFT": 0, "SPDIF_TX_PB_LEFT_3_reg_SPDIF_TX_PB_LEFT": 0, "SPDIF_TX_PB_LEFT_4_reg_SPDIF_TX_PB_LEFT": 0, "SPDIF_TX_PB_LEFT_5_reg_SPDIF_TX_PB_LEFT": 0, "SPDIF_TX_PB_LEFT_6_reg_SPDIF_TX_PB_LEFT": 0, "SPDIF_TX_PB_LEFT_7_reg_SPDIF_TX_PB_LEFT": 0, "SPDIF_TX_PB_LEFT_8_reg_SPDIF_TX_PB_LEFT": 0, "SPDIF_TX_PB_LEFT_9_reg_SPDIF_TX_PB_LEFT": 0, "SPDIF_TX_PB_LEFT_10_reg_SPDIF_TX_PB_LEFT": 0, "SPDIF_TX_PB_LEFT_11_reg_SPDIF_TX_PB_LEFT": 0, "SPDIF_TX_PB_RIGHT_0_reg_SPDIF_TX_PB_RIGHT": 0, "SPDIF_TX_PB_RIGHT_1_reg_SPDIF_TX_PB_RIGHT": 0, "SPDIF_TX_PB_RIGHT_2_reg_SPDIF_TX_PB_RIGHT": 0, "SPDIF_TX_PB_RIGHT_3_reg_SPDIF_TX_PB_RIGHT": 0, "SPDIF_TX_PB_RIGHT_4_reg_SPDIF_TX_PB_RIGHT": 0, "SPDIF_TX_PB_RIGHT_5_reg_SPDIF_TX_PB_RIGHT": 0, "SPDIF_TX_PB_RIGHT_6_reg_SPDIF_TX_PB_RIGHT": 0, "SPDIF_TX_PB_RIGHT_7_reg_SPDIF_TX_PB_RIGHT": 0, "SPDIF_TX_PB_RIGHT_8_reg_SPDIF_TX_PB_RIGHT": 0, "SPDIF_TX_PB_RIGHT_9_reg_SPDIF_TX_PB_RIGHT": 0, "SPDIF_TX_PB_RIGHT_10_reg_SPDIF_TX_PB_RIGHT": 0, "SPDIF_TX_PB_RIGHT_11_reg_SPDIF_TX_PB_RIGHT": 0, "SPDIF_TX_UD_LEFT_0_reg_SPDIF_TX_UD_LEFT": 0, "SPDIF_TX_UD_LEFT_1_reg_SPDIF_TX_UD_LEFT": 0, "SPDIF_TX_UD_LEFT_2_reg_SPDIF_TX_UD_LEFT": 0, "SPDIF_TX_UD_LEFT_3_reg_SPDIF_TX_UD_LEFT": 0, "SPDIF_TX_UD_LEFT_4_reg_SPDIF_TX_UD_LEFT": 0, "SPDIF_TX_UD_LEFT_5_reg_SPDIF_TX_UD_LEFT": 0, "SPDIF_TX_UD_LEFT_6_reg_SPDIF_TX_UD_LEFT": 0, "SPDIF_TX_UD_LEFT_7_reg_SPDIF_TX_UD_LEFT": 0, "SPDIF_TX_UD_LEFT_8_reg_SPDIF_TX_UD_LEFT": 0, "SPDIF_TX_UD_LEFT_9_reg_SPDIF_TX_UD_LEFT": 0, "SPDIF_TX_UD_LEFT_10_reg_SPDIF_TX_UD_LEFT": 0, "SPDIF_TX_UD_LEFT_11_reg_SPDIF_TX_UD_LEFT": 0, "SPDIF_TX_UD_RIGHT_0_reg_SPDIF_TX_UD_RIGHT": 0, "SPDIF_TX_UD_RIGHT_1_reg_SPDIF_TX_UD_RIGHT": 0, "SPDIF_TX_UD_RIGHT_2_reg_SPDIF_TX_UD_RIGHT": 0, "SPDIF_TX_UD_RIGHT_3_reg_SPDIF_TX_UD_RIGHT": 0, "SPDIF_TX_UD_RIGHT_4_reg_SPDIF_TX_UD_RIGHT": 0, "SPDIF_TX_UD_RIGHT_5_reg_SPDIF_TX_UD_RIGHT": 0, "SPDIF_TX_UD_RIGHT_6_reg_SPDIF_TX_UD_RIGHT": 0, "SPDIF_TX_UD_RIGHT_7_reg_SPDIF_TX_UD_RIGHT": 0, "SPDIF_TX_UD_RIGHT_8_reg_SPDIF_TX_UD_RIGHT": 0, "SPDIF_TX_UD_RIGHT_9_reg_SPDIF_TX_UD_RIGHT": 0, "SPDIF_TX_UD_RIGHT_10_reg_SPDIF_TX_UD_RIGHT": 0, "SPDIF_TX_UD_RIGHT_11_reg_SPDIF_TX_UD_RIGHT": 0, "SPDIF_TX_VB_LEFT_0_reg_SPDIF_TX_VB_LEFT": 0, "SPDIF_TX_VB_LEFT_1_reg_SPDIF_TX_VB_LEFT": 0, "SPDIF_TX_VB_LEFT_2_reg_SPDIF_TX_VB_LEFT": 0, "SPDIF_TX_VB_LEFT_3_reg_SPDIF_TX_VB_LEFT": 0, "SPDIF_TX_VB_LEFT_4_reg_SPDIF_TX_VB_LEFT": 0, "SPDIF_TX_VB_LEFT_5_reg_SPDIF_TX_VB_LEFT": 0, "SPDIF_TX_VB_LEFT_6_reg_SPDIF_TX_VB_LEFT": 0, "SPDIF_TX_VB_LEFT_7_reg_SPDIF_TX_VB_LEFT": 0, "SPDIF_TX_VB_LEFT_8_reg_SPDIF_TX_VB_LEFT": 0, "SPDIF_TX_VB_LEFT_9_reg_SPDIF_TX_VB_LEFT": 0, "SPDIF_TX_VB_LEFT_10_reg_SPDIF_TX_VB_LEFT": 0, "SPDIF_TX_VB_LEFT_11_reg_SPDIF_TX_VB_LEFT": 0, "SPDIF_TX_VB_RIGHT_0_reg_SPDIF_TX_VB_RIGHT": 0, "SPDIF_TX_VB_RIGHT_1_reg_SPDIF_TX_VB_RIGHT": 0, "SPDIF_TX_VB_RIGHT_2_reg_SPDIF_TX_VB_RIGHT": 0, "SPDIF_TX_VB_RIGHT_3_reg_SPDIF_TX_VB_RIGHT": 0, "SPDIF_TX_VB_RIGHT_4_reg_SPDIF_TX_VB_RIGHT": 0, "SPDIF_TX_VB_RIGHT_5_reg_SPDIF_TX_VB_RIGHT": 0, "SPDIF_TX_VB_RIGHT_6_reg_SPDIF_TX_VB_RIGHT": 0, "SPDIF_TX_VB_RIGHT_7_reg_SPDIF_TX_VB_RIGHT": 0, "SPDIF_TX_VB_RIGHT_8_reg_SPDIF_TX_VB_RIGHT": 0, "SPDIF_TX_VB_RIGHT_9_reg_SPDIF_TX_VB_RIGHT": 0, "SPDIF_TX_VB_RIGHT_10_reg_SPDIF_TX_VB_RIGHT": 0, "SPDIF_TX_VB_RIGHT_11_reg_SPDIF_TX_VB_RIGHT": 0, "PLL_CTRL0_reg_PLL_FBDIVIDER": 96, "PLL_CTRL0_regRESERVED2 Reserved": 0, "PLL_CTRL1_reg_PLL_DIV": "Divide by 4", "PLL_CTRL1_regRESERVED3 Reserved": 0, "PLL_CLK_SRC_reg_CLKSRC": "PLL clock", "PLL_CLK_SRC_regRESERVED4 Reserved": 0, "MCLK_OUT_reg_CLKOUT_ENABLE": "CLKOUT enabled", "MCLK_OUT_reg_CLKOUT_RATE": "Base_Fs x 256 (12.288 MHz for 48 kHz)", "MCLK_OUT_regRESERVED7 Reserved": 0, "PLL_ENABLE_reg_PLL_ENABLE": "Enabled", "PLL_ENABLE_regRESERVED5 Reserved": 0, "HIBERNATE_reg_HIBERNATE": "Not hibernating", "HIBERNATE_regRESERVED15 Reserved": 0, "START_CORE_reg_START_CORE": "Core is stopped", "START_CORE_regRESERVED17 Reserved": 0, "CORE_STATUS_reg_CORE_STATUS": "Core is not running", "CORE_STATUS_regRESERVED19 Reserved": 0, "PLL_LOCK_reg_PLL_LOCK": "PLL unlocked", "PLL_LOCK_regRESERVED6 Reserved": 0 }, "Angle": 0.0, "Position": { "X": 308.0, "Y": 321.0 }, "Size": { "Height": 163.0, "Width": 116.0 }, "Label": "ADAU1452_0", "WritableChannels": [], "WritableShapes": [ { "PluginName": "AnalogDevices.Plugins.Cores.ADAU145xCore_v1.0.0.0", "Name": "ADAU145xCore", "InterfaceType": "AnalogDevices.TypeDefinitions.Plugins.ICore", "Uid": "ADAU145xCore_0", "WritableProperties": { "IsRemovable": true, "RestrictShape": false, "BoardKey": "", "IsLocked": false, "EncryptedString": "", "CoreName": "ADAU1452" }, "Angle": 0.0, "Position": { "X": 0.0, "Y": 0.0 }, "Size": { "Height": 1.0, "Width": 1.0 }, "Label": "ADAU145xCore_0", "WritableChannels": [], "WritableShapes": [ { "PluginName": "AnalogDevices.Plugins.Schematics.ADAU145xSchematic_v1.0.0.0", "Name": "ADAU145xSchematic", "InterfaceType": "AnalogDevices.TypeDefinitions.Plugins.ISchematic", "Uid": "ADAU145xSchematic_0", "WritableProperties": { "IsRemovable": true, "RestrictShape": false, "BoardKey": "", "IsLocked": false, "EncryptedString": "", "CanvasSize": { "$type": "AnalogDevices.TypeDefinitions.Size, TypeDefinitions", "Height": 1920.0, "Width": 1080.0 }, "IsOverrunCodeEn": false, "OverrunCodeAddr": 0, "MaxCycles": "0", "FrameWorkList": { "$type": "System.Collections.Generic.List`1[[System.String, mscorlib]], mscorlib", "$values": [] }, "OverrunErrorCounterVariables": { "$type": "System.Collections.Generic.List`1[[System.String, mscorlib]], mscorlib", "$values": [] }, "OverrunErrorCounterAddr": { "$type": "System.Collections.Generic.List`1[[System.Int32, mscorlib]], mscorlib", "$values": [] }, "VariantEditorMemorySize": 1048576, "VariantEditorProtocol": "SPI", "VariantEditorPageSize": 256, "VariantEditorWriteSpeed": 10000, "VariantEditorNumAddressBytes": 3, "VariantEditorSPIMode": "SPIMode3", "VariantEditorSPIReadInstruction": 3, "VariantEditorModeCount": 0, "VariantEditorCurrentModeName": "", "VariantEditorSelfbootImageStartAddress": "0x00000", "VariantEditorSelfbootImageEndAddress": "0xFFFFFFFF", "VariantEditorAutoCalculateAddresses": true, "VariantEditorEnableVariantParamCopy": true, "VariantEditorSelectedModeIndex": 0, "VariantEditorSerializedModesData": "[]", "VariantEditorDownloadToTarget": false, "VariantEditorEEPROMAddressCalc": false, "VariantEditorGPIOSelDictionary": { "$type": "System.Collections.Generic.Dictionary`2[[System.String, mscorlib],[System.Boolean, mscorlib]], mscorlib", "GPIO0": false, "GPIO1": false, "GPIO2": false, "GPIO3": false, "GPIO4": false, "GPIO5": false, "GPIO6": true, "GPIO7": true, "GPIO8": false, "GPIO9": false, "GPIO10": false, "GPIO11": false, "GPIO12": false, "GPIO13": false, "GPIO14": false, "GPIO15": false, "GPIO16": false, "GPIO17": false, "GPIO18": false, "GPIO19": false, "GPIO20": false, "GPIO21": false, "GPIO22": false, "GPIO23": false, "GPIO24": false, "GPIO25": false }, "VariantEditorIsLoadEEPROM": false, "VariantEditorIsCompileUsingVariantCode": true, "PMCheckSumAddr": 0, "PmExpected": "0", "Dm0Expected": "0", "Dm1Expected": "0", "BaseAddress": 24585, "SerializedEntries": "", "TableLength": 5, "PageCount": 1, "IPATStartAddress": 24585, "CurrentPageNo": 1, "NoOfTriggerLoads": 1, "SchematicParamList": "", "EnMallocFreeBP": true, "EnClearUnusedMem": false, "EnCaptureMemDetails": false, "EnOverrunMonitor": false, "EnDMRemvZeroInit": false, "DisableRegisterDownload": false, "DisablePLLReset": false, "EnableSchematicVersion": false, "EnableChecksum": false, "EnableVariantEditor": false, "EnableIPAT": false, "Input0to15Used": true, "Input16to31Used": false, "Input32to39Used": false, "Input40to47Used": false, "OutputCh0": true, "OutputCh1": true, "OutputCh2": false, "OutputCh3": false, "OutputCh4": false, "OutputCh5": false, "OutputCh6": false, "OutputCh7": false, "OutputCh8": false, "OutputCh9": false, "OutputCh10": false, "OutputCh11": false, "OutputCh12": false, "OutputCh13": false, "OutputCh14": false, "OutputCh15": false, "OutputCh16": false, "OutputCh17": false, "OutputCh18": false, "OutputCh19": false, "OutputCh20": false, "OutputCh21": false, "OutputCh22": false, "OutputCh23": false, "OutputCh24": false, "OutputCh25": false, "OutputCh26": false, "OutputCh27": false, "OutputCh28": false, "OutputCh29": false, "OutputCh30": false, "OutputCh31": false, "OutputCh32": false, "OutputCh33": false, "OutputCh34": false, "OutputCh35": false, "OutputCh36": false, "OutputCh37": false, "OutputCh38": false, "OutputCh39": false, "OutputCh40": false, "OutputCh41": false, "OutputCh42": false, "OutputCh43": false, "OutputCh44": false, "OutputCh45": false, "OutputCh46": false, "OutputCh47": false, "ASRCInputUsed": false, "ASRCGainInputUsed": false, "MicInputUsed": false, "OutputSPDIFCh0": false, "OutputSPDIFCh1": false, "OutputSPDIFCh2": false, "OutputASRCCh0": false, "OutputASRCCh1": false, "OutputASRCCh2": false, "OutputASRCCh3": false, "OutputASRCCh4": false, "OutputASRCCh5": false, "OutputASRCCh6": false, "OutputASRCCh7": false, "OutputASRCCh8": false, "OutputASRCCh9": false, "OutputASRCCh10": false, "OutputASRCCh11": false, "OutputASRCCh12": false, "OutputASRCCh13": false, "OutputASRCCh14": false, "OutputASRCCh15": false, "GPIOCh0": false, "GPIOCh1": false, "GPIOCh2": false, "GPIOCh3": false, "GPIOCh4": false, "GPIOCh5": false, "GPIOCh6": false, "GPIOCh7": false, "GPIOCh8": false, "GPIOCh9": false, "GPIOCh10": false, "GPIOCh11": false, "GPIOCh12": false, "GPIOCh13": false, "GPIOCh14": false, "GPIOCh15": false, "GPIOCh16": false, "GPIOCh17": false, "GPIOCh18": false, "GPIOCh19": false, "GPIOCh20": false, "GPIOCh21": false, "GPIOCh22": false, "GPIOCh23": false, "GPIOCh24": false, "GPIOCh25": false, "IFIPCh0": false, "IFIPCh1": false, "IFIPCh2": false, "IFIPCh3": false, "IFIPCh4": false, "IFIPCh5": false, "IFIPCh6": false, "IFIPCh7": false, "IFOPCh0": false, "IFOPCh1": false, "IFOPCh2": false, "IFOPCh3": false, "IFOPCh4": false, "IFOPCh5": false, "IFOPCh6": false, "IFOPCh7": false, "AUX_ADC_0": false, "AUX_ADC_1": false, "AUX_ADC_2": false, "AUX_ADC_3": false, "AUX_ADC_4": false, "AUX_ADC_5": false, "AUX_ADC_6": false, "AUX_ADC_7": false, "IRCh0": false, "IRCh1": false, "IRCh2": false, "IRCh3": false, "IRCh4": false, "IRCh5": false, "IRCh6": false, "IRCh7": false, "IRCh8": false, "IRCh9": false, "IRCh10": false, "IRCh11": false, "IRCh12": false, "IRCh13": false, "IRCh14": false, "IRCh15": false, "IRCh16": false, "IRCh17": false, "IRCh18": false, "IRCh19": false, "IWCh0": false, "IWCh1": false, "IWCh2": false, "IWCh3": false, "IWCh4": false, "IWCh5": false, "IWCh6": false, "IWCh7": false, "IWCh8": false, "IWCh9": false, "IWCh10": false, "IWCh11": false, "IWCh12": false, "IWCh13": false, "IWCh14": false, "IWCh15": false, "IWCh16": false, "IWCh17": false, "IWCh18": false, "IWCh19": false, "CoreName": "ADAU1452", "SafeLoadDataStartAddress": 0, "SafeLoadAddressStartAddress": 0, "SafeLoadSize": 0, "FrameworkSelection": "Beginning", "FrameworkASMCode": "$region // @Autogenerated Macro definitions\r\n#define DIGIN_0 0xFC40\r\n#define DIGIN_1 0xFC41\r\n#define DIGIN_2 0xFC42\r\n#define DIGIN_3 0xFC43\r\n#define DIGIN_4 0xFC44\r\n#define DIGIN_5 0xFC45\r\n#define DIGIN_6 0xFC46\r\n#define DIGIN_7 0xFC47\r\n#define DIGIN_8 0xFC48\r\n#define DIGIN_9 0xFC49\r\n#define DIGIN_10 0xFC4A\r\n#define DIGIN_11 0xFC4B\r\n#define DIGIN_12 0xFC4C\r\n#define DIGIN_13 0xFC4D\r\n#define DIGIN_14 0xFC4E\r\n#define DIGIN_15 0xFC4F\r\n#define DIGIN_16 0xFC50\r\n#define DIGIN_17 0xFC51\r\n#define DIGIN_18 0xFC52\r\n#define DIGIN_19 0xFC53\r\n#define DIGIN_20 0xFC54\r\n#define DIGIN_21 0xFC55\r\n#define DIGIN_22 0xFC56\r\n#define DIGIN_23 0xFC57\r\n#define DIGIN_24 0xFC58\r\n#define DIGIN_25 0xFC59\r\n#define DIGIN_26 0xFC5A\r\n#define DIGIN_27 0xFC5B\r\n#define DIGIN_28 0xFC5C\r\n#define DIGIN_29 0xFC5D\r\n#define DIGIN_30 0xFC5E\r\n#define DIGIN_31 0xFC5F\r\n#define DIGIN_32 0xFC60\r\n#define DIGIN_33 0xFC61\r\n#define DIGIN_34 0xFC62\r\n#define DIGIN_35 0xFC63\r\n#define DIGIN_36 0xFC64\r\n#define DIGIN_37 0xFC65\r\n#define DIGIN_38 0xFC66\r\n#define DIGIN_39 0xFC67\r\n#define DIGIN_40 0xFC68\r\n#define DIGIN_41 0xFC69\r\n#define DIGIN_42 0xFC6A\r\n#define DIGIN_43 0xFC6B\r\n#define DIGIN_44 0xFC6C\r\n#define DIGIN_45 0xFC6D\r\n#define DIGIN_46 0xFC6E\r\n#define DIGIN_47 0xFC6F\r\n#define DIGOUT_0 0xFCC0\r\n#define DIGOUT_1 0xFCC1\r\n#define DIGOUT_2 0xFCC2\r\n#define DIGOUT_3 0xFCC3\r\n#define DIGOUT_4 0xFCC4\r\n#define DIGOUT_5 0xFCC5\r\n#define DIGOUT_6 0xFCC6\r\n#define DIGOUT_7 0xFCC7\r\n#define DIGOUT_8 0xFCC8\r\n#define DIGOUT_9 0xFCC9\r\n#define DIGOUT_10 0xFCCA\r\n#define DIGOUT_11 0xFCCB\r\n#define DIGOUT_12 0xFCCC\r\n#define DIGOUT_13 0xFCCD\r\n#define DIGOUT_14 0xFCCE\r\n#define DIGOUT_15 0xFCCF\r\n#define DIGOUT_16 0xFCD0\r\n#define DIGOUT_17 0xFCD1\r\n#define DIGOUT_18 0xFCD2\r\n#define DIGOUT_19 0xFCD3\r\n#define DIGOUT_20 0xFCD4\r\n#define DIGOUT_21 0xFCD5\r\n#define DIGOUT_22 0xFCD6\r\n#define DIGOUT_23 0xFCD7\r\n#define DIGOUT_24 0xFCD8\r\n#define DIGOUT_25 0xFCD9\r\n#define DIGOUT_26 0xFCDA\r\n#define DIGOUT_27 0xFCDB\r\n#define DIGOUT_28 0xFCDC\r\n#define DIGOUT_29 0xFCDD\r\n#define DIGOUT_30 0xFCDE\r\n#define DIGOUT_31 0xFCDF\r\n#define DIGOUT_32 0xFCE0\r\n#define DIGOUT_33 0xFCE1\r\n#define DIGOUT_34 0xFCE2\r\n#define DIGOUT_35 0xFCE3\r\n#define DIGOUT_36 0xFCE4\r\n#define DIGOUT_37 0xFCE5\r\n#define DIGOUT_38 0xFCE6\r\n#define DIGOUT_39 0xFCE7\r\n#define DIGOUT_40 0xFCE8\r\n#define DIGOUT_41 0xFCE9\r\n#define DIGOUT_42 0xFCEA\r\n#define DIGOUT_43 0xFCEB\r\n#define DIGOUT_44 0xFCEC\r\n#define DIGOUT_45 0xFCED\r\n#define DIGOUT_46 0xFCEE\r\n#define DIGOUT_47 0xFCEF\r\n#define GPIO_IN 0xF530\r\n#define GPIO_OUT 0xF520\r\n#define SPDIF_IN 0xFC70\r\n#define SPDIF_OUT 0xFCF0\r\n#define DIGMIC_IN 0xFC72\r\n#define ASRC_IN 0xFC30\r\n#define ASRC_OUT 0xFCB0\r\n#define AUX_ADC 0xF5A0\r\n#define INT_BASE_ADDR 0xFFC0\r\n#define INT_BLOCK_ADDR 0xFFC0\r\n#define INT_FRAME_ADDR 0xFFC1\r\n#define INT_READ_ADDR 0xFFC2\r\n#define INT_WRITE_ADDR 0xFFC3\r\n#define INT_I2C_ADDR 0xFFC4\r\n#define INT_SPI_ADDR 0xFFC5\r\n#define INT_DISABLE 0xFFD0\r\n#define INT_MASK 0xFFD1\r\n#define INT_CLEAR 0xFFD2\r\n#define INT_BLOCK_ENABLE 0xF450\r\n#define INT_BLOCK_COUNT 0xF451\r\n#define I2C_SPI_USAGE 0xFFA0\r\n#define I2C_SPI_SPEED 0xFFA1\r\n#define I2C_SPI_DONE 0xFFA2\r\n#define I2C_ERROR 0xFFA3\r\n#define I2C_SPI_ADDRESS_BYTES 0xFFA4\r\n#define I2C_SPI_ADDRESS 0xFFA5\r\n#define I2C_SPI_SLAVE 0xFFA6\r\n#define I2C_SPI_DATA_BYTES 0xFFA7\r\n#define I2C_SPI_DATA 0xFFA8\r\n#define I2C_SPI_MODE 0xFFAC\r\n#define EXP2 0xFD00\r\n#define EXP2_RESULT 0xFD04\r\n#define SQRT 0xFD10\r\n#define SQRT_RESULT_INT 0xFD12\r\n#define SQRT_RESULT 0xFD14\r\n#define FAST_SQRT 0xFD18\r\n#define FAST_SQRT_RESULT_INT 0xFD1A\r\n#define FAST_SQRT_RESULT 0xFD1C\r\n#define LOG2 0xFD20\r\n#define LOG2_NORM 0xFD24\r\n#define LOG2_RESULT_INT 0xFD28\r\n#define LOG2_RESULT_FRAC 0xFD29\r\n#define LOG2_RESULT 0xFD2A\r\n#define RAND_RESET 0xFD30\r\n#define RAND_SEED 0xFD31\r\n#define RAND_TRI_SEED 0xFD32\r\n#define RAND_SIGN 0xFD33\r\n#define RAND_UNSIGN 0xFD34\r\n#define RAND_DOT 0xFD35\r\n#define RAND_SIGN_NR 0xFD36\r\n#define RAND_UNSIGN_NR 0xFD37\r\n#define RAND_DOT_NR 0xFD38\r\n#define RAND_TRI_SIGN 0xFD39\r\n#define RAND_TRI_UNSIGN 0xFD3A\r\n#define RAND_TRI_DOT 0xFD3B\r\n#define RAND_TRI_SIGN_NR 0xFD3C\r\n#define RAND_TRI_UNSIGN_NR 0xFD3D\r\n#define RAND_TRI_DOT_NR 0xFD3E\r\n#define DIV_NUM_A 0xFD60\r\n#define DIV_NUM_B 0xFD62\r\n#define DIV_DEN_A 0xFD64\r\n#define DIV_DEN_B 0xFD65\r\n#define DIV_RESULT_INT 0xFD66\r\n#define DIV_RESULT 0xFD68\r\n#define DIV_DIV0 0xFD6C\r\n#define SLEW_MODE0 0xFD80\r\n#define SLEW_MODE1 0xFD81\r\n#define SLEW_MODE2 0xFD82\r\n#define SLEW_MODE3 0xFD83\r\n#define SLEW_TARGET0 0xFD84\r\n#define SLEW_TARGET1 0xFD88\r\n#define SLEW_TARGET2 0xFD8C\r\n#define SLEW_TARGET3 0xFD90\r\n#define SLEW_CURRENT 0xFD94\r\n#define SLEW_STEP_IN 0xFD98\r\n#define SLEW_STEP_OUT 0xFD9C\r\n#define SLEW_NEXT 0xFDA0\r\n#define SIN_0 0xC000\r\n#define COS_0 0xC800\r\n#define TWIDDLE_0 0xD000\r\n#define TAN_0 0xD800\r\n#define TANH_0 0xDA00\r\n#define P2_POW_M24 0xDC00\r\n#define P2_POW_M23 0xDC02\r\n#define P2_POW_M22 0xDC04\r\n#define P2_POW_M21 0xDC06\r\n#define P2_POW_M20 0xDC08\r\n#define P2_POW_M19 0xDC0A\r\n#define P2_POW_M18 0xDC0C\r\n#define P2_POW_M17 0xDC0E\r\n#define P2_POW_M16 0xDC10\r\n#define P2_POW_M15 0xDC12\r\n#define P2_POW_M14 0xDC14\r\n#define P2_POW_M13 0xDC16\r\n#define P2_POW_M12 0xDC18\r\n#define P2_POW_M11 0xDC1A\r\n#define P2_POW_M10 0xDC1C\r\n#define P2_POW_M9 0xDC1E\r\n#define P2_POW_M8 0xDC20\r\n#define P2_POW_M7 0xDC22\r\n#define P2_POW_M6 0xDC24\r\n#define P2_POW_M5 0xDC26\r\n#define P2_POW_M4 0xDC28\r\n#define P2_POW_M3 0xDC2A\r\n#define P2_POW_M2 0xDC2C\r\n#define P2_POW_M1 0xDC2E\r\n#define ONE 0xDC30\r\n#define P2_POW_P0 0xDC30\r\n#define P2_POW_P1 0xDC32\r\n#define P2_POW_P2 0xDC34\r\n#define P2_POW_P3 0xDC36\r\n#define P2_POW_P4 0xDC38\r\n#define P2_POW_P5 0xDC3A\r\n#define P2_POW_P6 0xDC3C\r\n#define P2_POW_P7 0xDC3E\r\n#define M2_POW_M24 0xDC40\r\n#define M2_POW_M23 0xDC42\r\n#define M2_POW_M22 0xDC44\r\n#define M2_POW_M21 0xDC46\r\n#define M2_POW_M20 0xDC48\r\n#define M2_POW_M19 0xDC4A\r\n#define M2_POW_M18 0xDC4C\r\n#define M2_POW_M17 0xDC4E\r\n#define M2_POW_M16 0xDC50\r\n#define M2_POW_M15 0xDC52\r\n#define M2_POW_M14 0xDC54\r\n#define M2_POW_M13 0xDC56\r\n#define M2_POW_M12 0xDC58\r\n#define M2_POW_M11 0xDC5A\r\n#define M2_POW_M10 0xDC5C\r\n#define M2_POW_M9 0xDC5E\r\n#define M2_POW_M8 0xDC60\r\n#define M2_POW_M7 0xDC62\r\n#define M2_POW_M6 0xDC64\r\n#define M2_POW_M5 0xDC66\r\n#define M2_POW_M4 0xDC68\r\n#define M2_POW_M3 0xDC6A\r\n#define M2_POW_M2 0xDC6C\r\n#define M2_POW_M1 0xDC6E\r\n#define M2_POW_P0 0xDC70\r\n#define M2_POW_P1 0xDC72\r\n#define M2_POW_P2 0xDC74\r\n#define M2_POW_P3 0xDC76\r\n#define M2_POW_P4 0xDC78\r\n#define M2_POW_P5 0xDC7A\r\n#define M2_POW_P6 0xDC7C\r\n#define M2_POW_P7 0xDC7E\r\n#define MASK_1BIT 0xDC80\r\n#define MASK_2BIT 0xDC82\r\n#define MASK_3BIT 0xDC84\r\n#define MASK_4BIT 0xDC86\r\n#define MASK_5BIT 0xDC88\r\n#define MASK_6BIT 0xDC8A\r\n#define MASK_7BIT 0xDC8C\r\n#define MASK_8BIT 0xDC8E\r\n#define MASK_9BIT 0xDC90\r\n#define MASK_10BIT 0xDC92\r\n#define MASK_11BIT 0xDC94\r\n#define MASK_12BIT 0xDC96\r\n#define MASK_13BIT 0xDC98\r\n#define MASK_14BIT 0xDC9A\r\n#define MASK_15BIT 0xDC9C\r\n#define MASK_16BIT 0xDC9E\r\n#define MASK_17BIT 0xDCA0\r\n#define MASK_18BIT 0xDCA2\r\n#define MASK_19BIT 0xDCA4\r\n#define MASK_20BIT 0xDCA6\r\n#define MASK_21BIT 0xDCA8\r\n#define MASK_22BIT 0xDCAA\r\n#define MASK_23BIT 0xDCAC\r\n#define MASK_24BIT 0xDCAE\r\n#define MASK_25BIT 0xDCB0\r\n#define MASK_26BIT 0xDCB2\r\n#define MASK_27BIT 0xDCB4\r\n#define MASK_28BIT 0xDCB6\r\n#define MASK_29BIT 0xDCB8\r\n#define MASK_30BIT 0xDCBA\r\n#define MASK_31BIT 0xDCBC\r\n#define MAX 0xDCC0\r\n#define MIN 0xDCC4\r\n#define PI 0xDCC8\r\n#define M_PI 0xDCCA\r\n#define PI_2 0xDCCC\r\n#define M_PI_2 0xDCCE\r\n#define SQRT2 0xDCD0\r\n#define M_SQRT2 0xDCD2\r\n#define P1_SQRT2 0xDCD4\r\n#define M1_SQRT2 0xDCD6\r\n#define LOG_INT_24 0xDCD8\r\n#define LOG_INT_56 0xDCDA\r\n#define ZERO 0xDCDC\r\n#define PTR_RESET 0xDCE0\r\n$endregion\r\n\n$region // @Autogenerated Initialization\r\n// Default Modulo Pointer Params\r\n\n// Clear all interrupt\r\ncli; //disable dsp core interrupts\r\nX0 = DM0[ZERO];\r\nDM0[INT_CLEAR] = X0; //disable all interrupts\r\nDM0[INT_DISABLE] = X0; //clear all disable masks\r\nDM0[INT_BLOCK_ENABLE] = X0; //disable the block interrupt generator\r\nDM0[0xF400] = X0; //clear interrupt suspend\r\n\n// Stack Init\r\nSB = 0;\r\nSP = 0;\r\nSL = 0;\r\n\n// Rounding -Inf (Truncation)\r\nRND = 0;\r\n$endregion\r\n\n$region // @Autogenerated Beginning Code\r\n// Zero-fill modulo memory\r\nP0.IBLM = DM0[PTR_RESET];\r\nX0 = DM0[ZERO];\r\n$endregion\r\n" }, "Angle": 0.0, "Position": { "X": 0.0, "Y": 0.0 }, "Size": { "Height": 1.0, "Width": 1.0 }, "Label": "ADAU145xSchematic_0", "WritableChannels": [ { "$type": "AnalogDevices.TypeDefinitions.Dom.SsprjDom.Internals.ChannelModel, TypeDefinitions", "WritableProperties": { "IsRemovable": true, "RestrictShape": false, "BoardKey": "", "IsLocked": false, "EncryptedString": "" }, "Uid": "SampleAnalog_0", "Name": "SampleAnalog", "PluginName": "AnalogDevices.Plugins.Channels.AudioChannel_v1.0.0.0", "InterfaceType": "AnalogDevices.TypeDefinitions.Plugins.IChannel", "LinkReference": { "$type": "System.Collections.ObjectModel.Collection`1[[System.String, mscorlib]], mscorlib", "$values": [ "Link_1", "Link_3", "Link_4" ] } }, { "$type": "AnalogDevices.TypeDefinitions.Dom.SsprjDom.Internals.ChannelModel, TypeDefinitions", "WritableProperties": { "IsRemovable": true, "RestrictShape": false, "BoardKey": "", "IsLocked": false, "EncryptedString": "" }, "Uid": "Analog_0", "Name": "Analog", "PluginName": "AnalogDevices.Plugins.Channels.AudioChannel_v1.0.0.0", "InterfaceType": "AnalogDevices.TypeDefinitions.Plugins.IChannel", "LinkReference": { "$type": "System.Collections.ObjectModel.Collection`1[[System.String, mscorlib]], mscorlib", "$values": [ "Link_2", "Link_5" ] } } ], "WritableShapes": [ { "PluginName": "AnalogDevices.Plugins.Algorithms.IO.Sigma300.Sample.Input0to15_v1.0.0.0", "Name": "Input 0-15", "InterfaceType": "AnalogDevices.TypeDefinitions.Plugins.IAlgorithm", "Uid": "Input0to15_0", "WritableProperties": { "IsRemovable": true, "RestrictShape": false, "BoardKey": "", "IsLocked": false, "EncryptedString": "", "RepCount": 1, "FS": 48000, "FSOut": 48000, "BlockSize": 64, "BlockSizeOut": 64, "ExcludeExport": false, "InUseCh0": true, "InUseCh1": true, "InUseCh2": false, "InUseCh3": false, "InUseCh4": false, "InUseCh5": false, "InUseCh6": false, "InUseCh7": false, "InUseCh8": false, "InUseCh9": false, "InUseCh10": false, "InUseCh11": false, "InUseCh12": false, "InUseCh13": false, "InUseCh14": false, "InUseCh15": false }, "Angle": 0.0, "Position": { "X": 0.0, "Y": 300.0 }, "Size": { "Height": 422.39999999999992, "Width": 93.0 }, "Label": "Input0to15_0", "WritableChannels": [], "WritableShapes": [], "WriteableLinks": [], "AltShapes": [], "PropertyPresets": {} }, { "PluginName": "AnalogDevices.Plugins.Algorithms.Sigma300.Output_v1.0.0.0", "Name": "Output", "InterfaceType": "AnalogDevices.TypeDefinitions.Plugins.IAlgorithm", "Uid": "Output_0", "WritableProperties": { "IsRemovable": true, "RestrictShape": false, "BoardKey": "", "IsLocked": false, "EncryptedString": "", "RepCount": 1, "FS": 48000, "FSOut": 48000, "BlockSize": 64, "BlockSizeOut": 64, "ExcludeExport": false, "SelectedOPChannel": "Ch0" }, "Angle": 0.0, "Position": { "X": 600.0, "Y": 300.0 }, "Size": { "Height": 83.0, "Width": 96.0 }, "Label": "Output_0", "WritableChannels": [], "WritableShapes": [], "WriteableLinks": [], "AltShapes": [], "PropertyPresets": {} }, { "PluginName": "AnalogDevices.Plugins.Algorithms.Sigma300.Output_v1.0.0.0", "Name": "Output", "InterfaceType": "AnalogDevices.TypeDefinitions.Plugins.IAlgorithm", "Uid": "Output_1", "WritableProperties": { "IsRemovable": true, "RestrictShape": false, "BoardKey": "", "IsLocked": false, "EncryptedString": "", "RepCount": 1, "FS": 48000, "FSOut": 48000, "BlockSize": 64, "BlockSizeOut": 64, "ExcludeExport": false, "SelectedOPChannel": "Ch1" }, "Angle": 0.0, "Position": { "X": 600.0, "Y": 600.0 }, "Size": { "Height": 83.0, "Width": 96.0 }, "Label": "Output_1", "WritableChannels": [], "WritableShapes": [], "WriteableLinks": [], "AltShapes": [], "PropertyPresets": {} }, { "PluginName": "AnalogDevices.Plugins.Visuals.Board_v1.0.0.0", "Name": "Hierarchy Board", "InterfaceType": "AnalogDevices.TypeDefinitions.Plugins.IVisual", "Uid": "Board_0", "WritableProperties": { "IsRemovable": true, "RestrictShape": false, "BoardKey": "", "IsLocked": false, "EncryptedString": "", "CanvasSize": { "$type": "AnalogDevices.TypeDefinitions.Size, TypeDefinitions", "Height": 1080.0, "Width": 1920.0 }, "FS": 48000, "HierarchyBoard": true, "Link": false, "BoardInput_0.Board_In": true, "BoardOutput_0.Board_Out": false }, "Angle": 0.0, "Position": { "X": 402.82352941176475, "Y": 142.58823529411768 }, "Size": { "Height": 128.0, "Width": 116.0 }, "Label": "Board_0", "WritableChannels": [], "WritableShapes": [ { "PluginName": "AnalogDevices.Plugins.Visuals.BoardInput_v1.0.0.0", "Name": "Board Input", "InterfaceType": "AnalogDevices.TypeDefinitions.Plugins.IBoardElement", "Uid": "BoardInput_0", "WritableProperties": { "IsRemovable": true, "RestrictShape": false, "BoardKey": "", "IsLocked": false, "EncryptedString": "", "Link": false, "BoardInputAddition": true }, "Angle": 0.0, "Position": { "X": -388.0, "Y": 131.0 }, "Size": { "Height": 55.0, "Width": 88.336666666666673 }, "Label": "BoardInput_0", "WritableChannels": [], "WritableShapes": [], "WriteableLinks": [], "AltShapes": [], "PropertyPresets": {} }, { "PluginName": "AnalogDevices.Plugins.Visuals.BoardOutput_v1.0.0.0", "Name": "Board Output", "InterfaceType": "AnalogDevices.TypeDefinitions.Plugins.IBoardElement", "Uid": "BoardOutput_0", "WritableProperties": { "IsRemovable": true, "RestrictShape": false, "BoardKey": "", "IsLocked": false, "EncryptedString": "", "Link": false, "BoardOutputAddition": true }, "Angle": 0.0, "Position": { "X": 691.0, "Y": 131.0 }, "Size": { "Height": 55.0, "Width": 95.336666666666673 }, "Label": "BoardOutput_0", "WritableChannels": [], "WritableShapes": [], "WriteableLinks": [], "AltShapes": [], "PropertyPresets": {} }, { "PluginName": "AnalogDevices.Plugins.Algorithms.Gain.Sigma300.Sample.Gain_v1.0.0.0", "Name": "Gain", "InterfaceType": "AnalogDevices.TypeDefinitions.Plugins.IAlgorithm", "Uid": "Gain_0", "WritableProperties": { "IsRemovable": true, "RestrictShape": false, "BoardKey": "", "IsLocked": false, "EncryptedString": "", "RepCount": 1, "FS": 48000, "FSOut": 48000, "BlockSize": 64, "BlockSizeOut": 64, "ExcludeExport": false, "Gain": 1, "IsDB": false, "MaxLinearValue": 127.9999, "MinLinearValue": -128, "SetTunable": false, "NumChannels": 1, "SlewType": "No Slew", "CustomVal": 8330 }, "Angle": 0.0, "Position": { "X": 145.0, "Y": 141.0 }, "Size": { "Height": 123.0, "Width": 86.0 }, "Label": "Gain_0", "WritableChannels": [], "WritableShapes": [], "WriteableLinks": [], "AltShapes": [], "PropertyPresets": {} }, { "PluginName": "AnalogDevices.Plugins.Algorithms.ArithmeticAndLogic.Sigma300.Sample.SignalAdd2ch_v1.0.0.0", "Name": "2 Channel Signal Add", "InterfaceType": "AnalogDevices.TypeDefinitions.Plugins.IAlgorithm", "Uid": "SignalAdd2ch_0", "WritableProperties": { "IsRemovable": true, "RestrictShape": false, "BoardKey": "", "IsLocked": false, "EncryptedString": "", "RepCount": 1, "FS": 48000, "FSOut": 48000, "BlockSize": 64, "BlockSizeOut": 64, "ExcludeExport": false, "NumChannels": 1 }, "Angle": 0.0, "Position": { "X": 196.35294117647061, "Y": 397.2941176470589 }, "Size": { "Height": 69.0, "Width": 97.0 }, "Label": "SignalAdd2ch_0", "WritableChannels": [], "WritableShapes": [], "WriteableLinks": [], "AltShapes": [], "PropertyPresets": {} }, { "PluginName": "AnalogDevices.Plugins.Algorithms.Filters.Sigma300.Sample.GeneralFirstOrder_v1.0.0.0", "Name": "General EQ (1st Order)", "InterfaceType": "AnalogDevices.TypeDefinitions.Plugins.IAlgorithm", "Uid": "GeneralFirstOrder_0", "WritableProperties": { "IsRemovable": true, "RestrictShape": false, "BoardKey": "", "IsLocked": false, "EncryptedString": "", "RepCount": 1, "FS": 48000, "FSOut": 48000, "BlockSize": 64, "BlockSizeOut": 64, "ExcludeExport": false, "PrecisionType": "SinglePrecision", "NumStages": 1, "Frequency_Stage0": 1000, "Gain_Stage0": 0, "FilterType_Stage0": 2, "Enabled_Stage0": true, "Phase_Stage0": true, "SetTunable": false }, "Angle": 0.0, "Position": { "X": 85.0, "Y": 524.0 }, "Size": { "Height": 203.0, "Width": 156.0 }, "Label": "GeneralFirstOrder_0", "WritableChannels": [], "WritableShapes": [], "WriteableLinks": [], "AltShapes": [], "PropertyPresets": {} } ], "WriteableLinks": [ { "Uid": "Link_2", "SourceUid": "BoardInput_0", "SourcePinName": "Board_In", "TargetUid": "Gain_0", "TargetPinName": "Input", "LinkType": "Analog", "Points": [ { "X": 121.0, "Y": 158.5 }, { "X": 121.0, "Y": 202.5 } ] }, { "Uid": "Link_3", "SourceUid": "Gain_0", "SourcePinName": "Output", "TargetUid": "BoardOutput_0", "TargetPinName": "Board_Out", "LinkType": "SampleAnalog", "Points": [ { "X": 667.0, "Y": 202.5 }, { "X": 667.0, "Y": 158.5 } ] } ], "AltShapes": [], "PropertyPresets": {} } ], "WriteableLinks": [ { "Uid": "Link_1", "SourceUid": "Input0to15_0", "SourcePinName": "Ch1_out", "TargetUid": "Output_1", "TargetPinName": "Input", "LinkType": "SampleAnalog", "Points": [] }, { "Uid": "Link_4", "SourceUid": "Input0to15_0", "SourcePinName": "Ch0_out", "TargetUid": "Board_0", "TargetPinName": "BoardInput_0.Board_In", "LinkType": "SampleAnalog", "Points": [ { "X": 389.0, "Y": 358.66666666666663 }, { "X": 389.0, "Y": 206.58823529411768 } ] }, { "Uid": "Link_5", "SourceUid": "Board_0", "SourcePinName": "BoardOutput_0.Board_Out", "TargetUid": "Output_0", "TargetPinName": "Input", "LinkType": "Analog", "Points": [ { "X": 575.99999999999989, "Y": 206.58823529411768 }, { "X": 575.99999999999989, "Y": 341.5 } ] } ], "AltShapes": [], "PropertyPresets": {} } ], "WriteableLinks": [], "AltShapes": [], "PropertyPresets": {} } ], "WriteableLinks": [], "AltShapes": [], "PropertyPresets": {} }, { "PluginName": "AnalogDevices.Plugins.Memory.EEPROM_v1.0.0.0", "Name": "EEPROM", "InterfaceType": "AnalogDevices.TypeDefinitions.Plugins.IMemory", "Uid": "EEPROM_0", "WritableProperties": { "IsRemovable": true, "RestrictShape": false, "BoardKey": "", "IsLocked": false, "EncryptedString": "", "PlatformName": "EEPROM", "SlavePort": "SPI", "I2CSlaveAddress": "0xA0", "AddrboxEn": false, "MemoryUsed": 0, "MemSize": 128, "PageSize": 256, "_showReadWriteWndPw": 1, "MemorySpeed": 10000, "SPIWriteEnable": 6, "SPIWriteInstruction": 2, "SPIReadInstruction": 3, "SPINumAddressBytes": 3, "SPIErase": 199, "SPIMode": 1, "MemProtocol": 1, "SPIEraseTime": 5, "FileName": "", "AddrVisible": true, "BytesPerLine": 4, "DisplayText": "", "WriteThroughUSBPerformed": false, "WriteDatatoEEPROM": null, "ReadDataFromEEPROM": null }, "Angle": 0.0, "Position": { "X": 308.0, "Y": 584.529411764706 }, "Size": { "Height": 133.0, "Width": 116.0 }, "Label": "EEPROM_0", "WritableChannels": [], "WritableShapes": [], "WriteableLinks": [], "AltShapes": [], "PropertyPresets": {} }, { "PluginName": "AnalogDevices.Plugins.Visuals.UserComment_v1.0.0.0", "Name": "Comment", "InterfaceType": "AnalogDevices.TypeDefinitions.Plugins.IVisual", "Uid": "UserComment_1", "WritableProperties": { "IsRemovable": true, "RestrictShape": false, "BoardKey": "", "IsLocked": false, "EncryptedString": "", "CanvasSize": { "$type": "AnalogDevices.TypeDefinitions.Size, TypeDefinitions", "Height": 1080.0, "Width": 1920.0 }, "FS": 48000, "Link": false, "UserText": "ADAU1452 could be changed to I2C control via right click and select control port option. Once connected to I2C that seems to go away?\r\n\r\n That doesn't work for the EEPROM.\r\n" }, "Angle": 0.0, "Position": { "X": 572.88235294117658, "Y": 386.85999999999996 }, "Size": { "Height": 171.28000000000012, "Width": 821.35549872122738 }, "Label": "UserComment_1", "WritableChannels": [], "WritableShapes": [], "WriteableLinks": [], "AltShapes": [], "PropertyPresets": {} } ], "WriteableLinks": [], "AltShapes": [], "PropertyPresets": {} }, { "PluginName": "AnalogDevices.Plugins.Communication.USBi_v1.0.0.0", "Name": "USBi", "InterfaceType": "AnalogDevices.TypeDefinitions.Plugins.ICommunication", "Uid": "USBi_0", "WritableProperties": { "IsRemovable": true, "RestrictShape": false, "BoardKey": "", "IsLocked": false, "EncryptedString": "", "FirmwareVersion": "v1.5" }, "Angle": 0.0, "Position": { "X": 26.588235294117794, "Y": 264.41176470588232 }, "Size": { "Height": 113.0, "Width": 116.0 }, "Label": "USBi_0", "WritableChannels": [], "WritableShapes": [], "WriteableLinks": [], "AltShapes": [], "PropertyPresets": {} }, { "PluginName": "AnalogDevices.Plugins.Visuals.UserComment_v1.0.0.0", "Name": "Comment", "InterfaceType": "AnalogDevices.TypeDefinitions.Plugins.IVisual", "Uid": "UserComment_0", "WritableProperties": { "IsRemovable": true, "RestrictShape": false, "BoardKey": "", "IsLocked": false, "EncryptedString": "", "CanvasSize": { "$type": "AnalogDevices.TypeDefinitions.Size, TypeDefinitions", "Height": 1080.0, "Width": 1920.0 }, "FS": 48000, "Link": false, "UserText": "Target board has ADAU1452 & EEPROM connected via I2C to \"host\"" }, "Angle": 0.0, "Position": { "X": 56.0, "Y": 41.0 }, "Size": { "Height": 91.279999999999987, "Width": 437.7237851662403 }, "Label": "UserComment_0", "WritableChannels": [], "WritableShapes": [], "WriteableLinks": [], "AltShapes": [], "PropertyPresets": {} } ], "WriteableLinks": [ { "Uid": "Link_6", "SourceUid": "PC_0", "SourcePinName": "USB", "TargetUid": "USBi_0", "TargetPinName": "USB", "LinkType": "USB", "Points": [ { "X": 13.0, "Y": 288.26470588235293 }, { "X": 13.0, "Y": 320.91176470588232 } ] }, { "Uid": "Link_7", "SourceUid": "USBi_0", "SourcePinName": "I2C", "TargetUid": "CustomPlatform_0", "TargetPinName": "I2C Slave Port", "LinkType": "I2C", "Points": [ { "X": 236.0, "Y": 361.26890756302515 }, { "X": 236.0, "Y": 333.07843137254895 } ] } ], "AltShapes": [], "PropertyPresets": {} } }