ADAU1701 as I2S slave and Osc Sync
I have a question on ADAU1701 - not sure if this is right place... Newbie - sorry.
I have an instrumentation design needs 8xADAU1701 . Is it possible to synchronise the frame rates of these parts exactly - down a level that the I2S ports if outputting are synchronous? Will this just happen if common reset and clock them?
Further question related to sigmastudio sources for the above part. There is schematic object marked "sine tone with phase and gain". It could suit my purposes well but I have to know to what (time point) is the phase relative. There is no reset or ref pin on the gui object in the schematic - just an output. How is this meant to work.? Ideally I would like to sync it to one of the GPIO input pins and reset it.
hope im not too far off base with these Qs
Audio Signal Processors
SigmaDSP Audio Processors
adau1701
Hello lightwise,
I branched your discussion into a new topic. It was not the same question as the thread you posted it onto.
If you have multiple devices, and need to synchronize them, it can be done. Simply running them on the same master clock is not good enough. The internal PLLs may lock at slightly different times and so the sampling clock, the LRCLK, may be a few master clock cycles different.
So the way to do this is to do as you suggest which is to run them on the same Master Clock. Then if you operate the serial ports as slaves, then all the data will be transferred at the same time. The processing of the cores will all happen at the same time so it will all work. You can have one of the DSPs be the clock master and distribute the LRCLK and BCLK from that device or if you have something else in your system then it could be the master. I would use a clock distribution IC to buffer these clocks. Otherwise, you may have signal integrity issues especially if you use a higher sampling rate.
You other question about synchronizing the DSP Oscillator cell when it is running in different DSPs. The answer is you cannot. I seem to remember some threads where this was discussed. Do a search of the forum, I do not have time to do it right now. Others may chime in with suggestions.
Dave T
thanks Dave,
excellent answers - tho the second is not exactly what I wanted to hear. Apologies for posting in the wrong place - I am new to the engineerzone thing... To make matters worse - Ive just posted my questions again to another engineerzone area, just now, before seeing your reply.
I think that I should be able make the serial ports work as you suggest with the serial ports on my micro. So, I take it that once the PLL has settled down after reset that the parts will remain synchronous but possibly slightly out of phase wrt to Fs. - That will work fine in my app.
Regarding the Oscillator cell, I was screwing with a demo board and found that two separate cells within one device will run synchronously if 'programmed' (via sigmastudio) simultaneously. Interestingly, if I very very slightly alter the Freq of one 'on the fly' via SS it will gradually slide out of phase so it seems the phase info is preserved during the F change. If I programmed that aspect/ those registers/ in 8 devices simultaneously via SPI - would the cells in each then run synchronously across all devices. ? If yes - how close in phase (time) do you reckon?
I would test to confirm if you think it might work...
Lastly, is it possible / how do I / find the registers(or pointers) in the devices that are analogous to the parameters in the SigmaStudio blocks (e.g. Frequency of osc cell) so that I can subsequently change them on the fly... ??
whew
Dan, Lightwise
Hi Dave,
I know you told me not to do the OSC sync thing it but it does seem to work ... almost all of the time. I have a bunch of 5 carriers and demod carriers running synchronously in 8 ADAU1701s all driven from the same clock and running the same prog designed from SS. They way that I start it is to simultaneously program and start all APs in parallel over I2C after they have had a chance to reset.
The oscillators run synchronously quite perfectly 99% almost all times but one or more APs can be step-knocked out of phase (not freq) off by something , probably something that I am doing. I am finding it difficult to track what event I am doing that might causing it.
I do regularly read and write to individual and groups of ADAUs over I2C but am trying to identify what particular thing that I might be doing that would throw one OSC in one AP out of phase with another. I do not write to the oscillators at any stage to start, stop or modify any of their parameters. do you have any idea what might be affecting the phase of the Osc's or interrupting the running of the DSP loop.
Thanks 4 help
Dan
I did a search of the Forum but was not able to come up with any relevant threads . I would appreciate your help on that also.
Dan
This is one of our early SigmaDSPs and as such when you write to memory from the comms port it prevents the core from accessing memory for that instruction cycle. So this may be the issue? Try using Safeload writes for all writes to the device. These are done during the idle time between sample periods. It also prevents updates in the middle of the program when it is run for every sample period. This is a hunch but give it a try.
Dave T
Hello lightwise,
I put in "demodulator" and came up with a number of threads. You mentioned demodulating but never specified what type of demodulating?
https://ez.analog.com/dsp/sigmadsp/f/q-a/109328/adau-1701-4-channel-ssb-transreciver
https://ez.analog.com/dsp/sigmadsp/f/q-a/100078/ssb-modulator-upper-and-lower-sideband/298288#298288
https://ez.analog.com/dsp/sigmadsp/f/discussions/65679/a--1701-fm-mpx-demodulator
DaveT
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