CLKOUT on ADAU1467
I'm working on a system that provides usb-to-i2s bridge audio, where the usb chip is supposed to act as i2s slave. ADAU1467 will be the i2s master. Besides i2s bit and frame clocks, the usb chip also requires audio master clock for host feedback functionality. This audio master clock is either based on 44.1 or 48kHz, depending on sample rate from the usb host. So, it either requires 22.6 or 24.6MHz.
My question is whether it's feasible to switch the CLKOUT on the DSP between these two audio frequencies (22.6/24.6)? I'm thinking that the usb chip receives a sample rate from the usb host, determines if its based on 44.1 or 48 and send an i2c control command to the DSP so that it outputs correct CLKOUT.
Of course, I could always add a pll to the usb chip, but I wonder if it could be done with the dsp alone.
Thank's
AJ
Audio Signal Processors
adau1467
i2s
SigmaDSP Audio Processors
usb
No. See fig 20 in the data sheet.
Hello AJ,
Figure 20 shows the main PLL system and it is a little confusing in that the CLKOUT is actually taken from the output of the PLL and is a multiple of the divided MCLK. It was easier to show the frequency calculation the way it was drawn.
So in your design you may or may not be using ASRCs but in the end if you have to switch the master clock frequencies then using the CLKOUT is not a great way to do it. Each time you would have to shut off the PLL and restart it with new coefficients. I think the simpler way is to use an unused serial port BIT CLOCK output as a master clock to the USB device. The serial ports can come from different clock generators in the DSP so you can set one up for 44.1kHz base and the other for 48kHz base frequency.
By the way, What are the frequencies you need? Normally they are either 256 x fs or 512 x fs. It looks like you are looking for 512 x fs. So that would give you:
44.1kHZ x 512 = 22.5792 MHz
48 kHz x 512 = 24.576MHz.
So it looks like you rounded up.
I think this is the best way to do this because you have control over the frequency without having to stop the core and reboot the PLL.
Dave T
True. Haven't though that the BTCLK could be configured to run at such high frequencies.
Thank's
AJ
AJ,
I agree with David's answer. I want to point out that, for the clock output that is not a simple integer ratio of the crystal, there will be some jitter on the BCLK line, even when using the precision clock generator (clkgen3 has more bits in the calculation). You'll find that the LRCLK is quite stable, which is usually what matters most in an audio system. However, BCLK will be quantized to the clock generator's LSB.
Ken
Very useful information! Thank's Ken.
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