SigmaStudio: Can't save/reload design with heirarchy blocks using downsampling ADAU1452

Hello PolEx,

Sorry for the trouble. Can you zip up and attach the file?

I will see if I can duplicate this on my own but it would be faster if I had your file.

Thanks,

Dave T

Hello PolEx,

Also, can you tell me which version of SigmaStudio you are using?

Thanks!

Dave T

One more question,

Do you open the file by double clicking on the file or do you open SigmaStudio first then open the file?

Dave T

I'm using 4.1 but will try 4.2. I open the file by opening SS first, then File->Open-select filename. hw_polex_192_Current RevF.zip

Tried 4.2; same problem.

Also found that I had some obsolete algorithms. Updated them all; no change.

Hello PolEx,

Thanks for the additional info.

Are you using the built-in LPF that are in the down/up sampling blocks?

I was able to find some issues with the LPF implementation that I reported to the programming team. When I use an external LPF it all works fine. But, I have not been able to replicate the issue with saving the project and reopening.

Dave T

No, I don't use the built in LPF in either downsampling or upsampling. Not surprised you can't duplicate failure, because the only evidence of failure is in the actual performance of the code in situ. I do think if you compile it two different ways, one by just reading in the file and compiling it, and a second by following my work around, you will get diffferent output code. Maybe you can analyze it that way. Appreciate the help; sure wish someone could come up with a fix.

I think I may have come up with a lead on this. As a more permanent workaround, I thought that the problem was because the circuitry was in a Hierarchy Board, so I decided to move all the circuitry in the affected boards up to the main level schematic, i.e. flatten the design. To my surprise this did not cure the problem. But it was an important clue. Then, by the process of elimination, by re-instantiating one block at a time, I was able to find out which block is causing the trouble.

Turns out it is the Nth order filter block. if this block is included in the design, saved, reloaded, and compiled, it comes out wrong (not sure exactly what is wrong about it). After reloading the file, the Nth order filter block must be re-instantiated. Then it compiles properly.

Here's another thing I noted: The sample rate for the entire design is 192kHz. This section is running at 1/16th of that rate, or 12kHz. In order to get the fitler cutoff frequencies to come out right, I have to put a number in for the cutoff that is 16x the desired cutoff. So to get a cutoff of 1350Hz from these filters, I have to put in 21600kHz. maybe this is another clue to what is going wrong here.

One more note: You don't have to insert the Nth order filter from the Tool box; you can simply copy it (Ctrl-C) and paste it (CTRL-V), delete the original, and wire in the copy, and it all works fine.

Screwy, huh?

Ok, yet another thing I found: You can see the sample rate when you hover your mouse pointer over a wire. When you reload the file ('Broken' case), for Nth order fitlers in downsampled areas, both inputs and outputs will show 12KHz. But after you re-instantiate the Nth order filter ('Working' Case), the input shows 12KHz but the output shows 192Khz.

Something about the Nth order filter changes when it gets saved/reloaded.

Replaced the Nth order filters with FIRs. Problem solved!