ADAU145x/146x Master Slave I2S register setting

Hi

It is not clear in the data sheet what is the behavior of an I2S output channel when the configuration in SERIAL_BYTE_x_1 of the corresponding BCLK is set MASTER and LRCLK is set SLAVE ( linked to another channel with proper clock for LRCLK and BCLK).

In other words, is it possible to use a BLCK pin to issue a system clock (e.g. generated by CLK_GEN3) while having the corresponding I2S output channel fully clocked in slave mode from another Chanel?

Thanks a lot, as I do not see how to test this my eval board