1777 filter at 768 kHz
Hello:
I used the attached file to run a project that allows me to stimulate a filter and record the input and output of the filter. When I run this on a 1777 eval board at 768kHz with a parametric EQ filter, I have noticed that the actual response does not equal the response shown in sigmastudio's filter plot. In fact, the actual response looks like sigmastudio's response but with the frequency axis halved. For instance, using the attached file sigmastudio shows me a filter passing through -10 dB at 2kHz, while from my recordings of input and output I derive a filter response going through -10 dB at 1 kHz. Reading the filter coefficients out of memory and determining the expected response for a 768 kHz sample rate shows a filter going through -10dB at 2 kHz.
These data lead me to think the chip is not running at 768 kHz, but at 384 kHz.
Has anyone confirmed that at 768 kHz the 1777 filters perform as shown in sigmastudio?
Thanks for your time and attention,
HH
It occurred to me that dragging and dropping my project may not have attached the file in my previous post so I am attaching a zipped version here.
-HH
FilterCheck.zip
Hello HH,
You are running the converters at half speed because you are dividing the MCLK by 2.
Your project is setup to bypass the PLL so I assume you are using a crystal that is 12.288MHz as your MCLK input. In that case you must set both dividers after the PLL to divide by 1. You have the core set to 1 but not the MCLK to the main blocks, that one is set to divide by two. The main blocks are the serial ports and the converters.
If you use the PLL then the PLL output will be around 24.576MHz so then you need to divide by 2.
I think this should fix your problem.
By the way, I think this project was a little too complicated, I had trouble understanding the signal flow! Just joking! I like a simple projects, removes other possible issues. :)
Dave T
I was hoping it was an easy one!
Okay, so if I enable the PLL, and make no other changes, the filter response shown in sigmastudio should match the one I get by passing a wideband signal through and checking the output? And also, I will be able to run at a 768 kHz sample rate and have access to the full 32 instructions? (I am following the advice given in this link: https://ez.analog.com/dsp/sigmadsp/f/q-a/91234/adau1777-problem-with-more-than-16-instructions).
Thanks,
HH
Hello HH,
The thread you referenced has an answer that did not come from ADI. I will ask the person who supports this part more than I do to look into it. He is travelling right now so it might be a few days.
In that example he was using the PLL so the output was 24MHz. By still dividing the main blocks by two he was running the converters at the correct rate, he was running the core at a higher rate. The core rate controls the instructions per sample more than the actual sample rate. In your case you are bypassing the PLL and running at 12.288 MHz. By dividing the clock to the main blocks you are running at half the sample rate but your filters are designed to run at full rate so the frequencies are off by a factor of two. So you have to run the core undivided if you are not using the PLL and your crystal is 12.288MHz.
Dave T
Hello HH,
I looked into your SS project and it seems you are using crystal with oscillator enabled. Is this 12.288MHz?
For 768K operation, you will need 24.576MHz master clock and this will also enable you to get all 32 instructions in DSP.
To get the correct clock You have three options
1, Use 12.288MHz crystal with internal PLL. The PLL will multiply the clock to 24.576MHz.
2. Use 24.576MHz crystal then you do not need PLL and save some power.
3. Use external oscillator of 24.576MHz and then disable crystal oscillator and PLL to save more power.
I think getting the right clock frequency should fix your issue. I will test the project in a day or two and update you if I find anything more.
Regards
Rajeev
Please log in to reply.