ADAU1966

Hello Stephen,

Wow, this may be a little tricky to do. First question is what is the sampling rate? If it is 48kHz then this may be difficult with the PIC since the bitclock frequency will most likely be 24,576MHz.

How much do you know about TDM signals? I do not want to start really simple and insult your knowledge. If you are new to TDM then have you looked up info on Wiki?

I also need to know how many bits is the data?

This DAC is reasonably flexible.

Oh! One more question, will you be controlling the DAC using the PIC over SPI or I2C? This will mean you have more control over the settings. If you are using the stand-alone mode then your options are limited.

Thanks,

Dave T

Hi Dave,

In terms of sampling rate we don't want it, we are just trying to generate constant DC voltages and have not been able to find a 24bit DAC that does not seem to be designed for audio.

To answer your question about TDM, until I read the datasheet for this DAC I had never heard of it. I did a quick bit of googling and I am still not really clued up on how it works or how the waveform is meant to look, so feel free to insult my knowledge.

We need to write a 24 bit analogue value to each channel and have it stay there until the next value is written, which may be 2 hours later for example. Literally we want to use it to generate constant analogue voltages.

We can control the DAC via SPI.

Equally if you guys have a more suitable DAC for this application we are all ears ( as I mentioned this was chosen by our customer and we have no idea how/why he chose it).

Thanks,

Stephen

Hello Stephen,

I have had seen several customers use these for non-audio uses. I think the channels count and cost per channel is attractive. It also saves a lot of space on the PCB and keeps the parts count lower. Most of them were using it for low frequency signals that are DC to a few hertz for low frequency applications so their sampling rates were really low.

Before I go off on a discussion of the part directly, I can say a few things about TDM.

Have a look at this post I wrote a while back:

https://ez.analog.com/audio/f/discussions/3510/how-to-take-meaningful-screenshots-of-i2s-audio-signals

These screenshots are for an I2S signal which is a stereo signal with a specific setup of the clocks. TDM is much more open in that it can have many different clocking setups. I2S is a single case of TDM-2 with 32 bit-clocks per channel, with the data delayed from the Frame clock edge by one bit. Note: that LRCLK is short for Left/Right clock so it assumes a 50/50 duty cycle so the left channel is when the clock is low and the right channel is when it is high. In TDM there can be many channels so there it is called a frame clock. Either way the clock period is one sample period. The I2S is 50/50 duty cycle but TDM is often only a pulse, and usually that pulse is one bit-clock period wide. This marks the start of the sample period.

So the frequencies of these clocks is fairly simple to figure out. The Frame clock is the sample rate, The bit clock is used to clock in the data bits. If you recall studying shift registers in school using flip-flops, you had the serial data appearing on the first flop, then there was a clock pulse on the edge triggered flip-flop clock input. This would latch in the data and all the data would shift over by one flop. So this is the bit clock. It has nothing to do inside the part except for clocking the data into the shift register. So the frequency is dependent on the number of bits in the audio data slot and the number of channels present in each sample period.

Often the data slots are 32 bits long, left justified. So this means that you can insert 32/24/16 bits of audio without making any changes. So if you have 32 bit wide data slot and you have 8 channels of audio then the bitclock frequency will be the sampling rate * the slot width * the number of channels. So for 48kHz fs that would be 48,000 * 32 * 8 = 12.288MHz bit clock frequency.

Now on to your use. You clearly do not need a fast sampling rate. This part is able to lock the PLL to an LRCLK frequency but the datasheet does not say how low of a frequency you can use. One of our older parts could go down to 8kHz sampling rate so I expect this part to be similar. So below this rate you have to bypass the PLL and direct clock the part. So you will have to provide a Master Clock that is 512 x the sampling rate.

Now this part was meant to process audio so it uses a Sigma-Delta over sampling filter to produce the output. Sigma-Delta is not very good with DC, it can bounce around a little so you will not get 24 bits of resolution, you get realistically, 16 bits and maybe 20 bits. This may be good enough for your application. Another thing that affects the accuracy is the common mode reference generator. This is not designed to be super accurate since it is not very significant for audio. So it will drift slowly over time. It is possible on this part to use an external reference so this might be something to consider to improve the DC accuracy over time.

You also should ask the engineers in our precision converter group. They may have a solution for you. Then search for DC reference generators. Perhaps there is something there that would work for your application? Search the forum and ask questions in these other spaces.

Dave T