How to check the main clock is functioning
I have an ADAU1452 system with 24.576 xtal clk.
sigmastudio asks for a pll clock source (direct from MCLK pin or PLL), but I cannot find that switch in the datasheet.
sigmastudio fs is 96khz. the MCLK out is selected: baseclock out 24.576 for 48khz, and that is what I measure indeed.
master PLL is set to CTRL1:div8 and CTRL0: x 96 lock is indicated, I measure 2.07V on the pll node
now to set the clock generators:
I set gen1 M=3 N=1, this should get me a LRCK of 96Khz: 294.912 MHz ÷ 1024 × 1 ÷3 = 96khz
instead I measure on the sdataout 2 only 8Khz LRCK when a 2ch 32bit is selected, LRCK is master . only by changing the M and N, and changing the sdata Fs sampling rate to x* fs I get my required 96Khz LRCLK rate. how do I know the master PLL is running correctly , even if it shows "locked" ? something does not seem right here..
Audio Signal Processors
adau1452
SigmaDSP Audio Processors
the DSP draws about 80mW total on the1.2V and 3.3V rails together, as an indicator ofactual clock frequency.
Hello basreflex,
First of all I should tell you a little trick. If you want to know what register is being used when you select something in SigmaStudio, all you have to do is change the register and look at the Capture window to see what address was written to. Then search the datasheet for that address and you will most likely find it.
0xF002 is the PLL Clock Source Register. You do not want to use the direct MCLK selection. Even with a 24MHz clock the DSP will be running something like 12 times slower! The output of the PLL is a nominal ~294MHz. Huge difference from 24MHz.
So your settings of CTRL1 = 8 and CTRL0 = 96 is correct. That sets up the PLL to produce the correct system clock of 294.912 MHz. with the master clock you have.
The CLKOUT pin, called MCLK Out in SigmaStudio, is the output of the PLL. So the PLL pre-divider of "8" already corrected for your master clock frequency so now when you set the CLKOUT to be 24.576 for 48kHz you will get that frequency. So you have the correct PLL settings.
Now, unless you really need a different range of selection frequencies, I suggest you keep the default M & N settings for clock generator 1. This will give you the sampling rates that is listed in the datasheet and in SigmaStudio. So if you want 96kHz you select the 96kHz. Changing the default 6 to a 3 you are making the 48kHz setting be the setting for 96kHz. Your math is correct. So you say you are getting 8kHz?
Ah!! Here it is. You must be set to drive the system clock from the MCLK pin instead of the PLL output.
24.576MHZ / 1024 x1 /3 = 8kHZ.
Set register 0xF002 to be the PLL output.
Dave T
yep thanks a million, that did the trick, the sigmastudio decribes the 0xF002 switch as PLL clk source, in my interpretation as the source for the PLL: MCLK , tricky.
drop by for a glass of cava ? (spain)
Hello basereflex,
Yes, I agree with you that it is not the PLL clock source, it is the system clock source. The name is misleading but it is too late to go changing the datasheet.
I would love to go visit Spain some day! I lived in Europe for two years and traveled around a lot but never went to Spain. It was the summer of 1979 and terrorists had taken over a tourist train in Barcelona around the time I was travelling so I wisely avoided the area. Perhaps some day I will make it over there!
Dave T
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