Can VC Delay be put in program memory?
In SS4.2 ADAU1452 there is a block called "Multi-Tap Voltage Controlled Delay".
This block has 3 switches 0,1,PM.
Does this mean you can put the delay in DM0, DM1 or in Program Memory?
Unfortunately i did not find a documentation.
Any help appreciated.
Best regards
Bernd
Audio Signal Processors
adau1452
SigmaDSP Audio Processors
Yes. That is exactly what it means.
Ken
Ok thanks
Bernd
Ken or others: Hate to revive the dead, but I didn't see this asked or answered here:
If using PM for a Delay module, does that count against the PM MIPS while running?
I wouldn't really expect so, I mean, why have the 1462 otherwise since that just added memory (and spdif improvements) without increasing the core speed or the # of MIPS. But I don't know and haven't seen if the PM is dual-ported the same way that DM0 and DM1 are.
Please log in to reply.