How to boot dual-core application from non-default location in SPI Flash?
Thread Summary
The user asked how to boot a dual-core application from a non-default location in SPI Flash on a BF607 using CCES 2.8.3 and an ICE1000 emulator. The solution involved creating a single .ldr file for the dual-core application and ensuring only Core0 calls the rom_Boot function in the SSL project. Additionally, using adi_core_1_enable() in the main function of Core0 in the application project resolved the issue, allowing the SSL to boot the dual-core application successfully.AI Generated Content
Hi, All ADI experts
My question: how to boot dual-core application from non-default location in SPI Flash?
Environment: BF607 , CCES 2.8.3 , emulator ICE1000, the flash is wired to SPI0.
I wrote dual-core application: bf607_test_Core0 and bf607_test_Core1.The two application transfer data to each other by shared memory and the shared memory is a buffer allocated from a memory pool block at the section (0xc8080420-0xc8082c1f) which the two Cores can access both.
My CCES setup for dual core-application (in Post-build steps field) to produce the ldr file of dual core.
In property of core1 project, add a loader switch -NoFinalTag ../../bf607_test_Core1/Release/bf607_test_Core1.dxe.
If I run this application via Emulator: it works OK (both cores OK)
If I programmed ldr file of dual-core application into default location in SPI Flash (0x00000000) and press RESET : it works OK (both cores OK)
I programmed ldr file of dual-core application into any different location ( i.e. 0x00014000 ) and I wrote a dual-core second_stage_loader(ssl): bf607_SSL_Core0 and bf607_SSL_Core1 similarly. The two application of ssl also transfer data to each other by shared memory. I want to use ssl to boot application. Each core use rom_Boot () function to boot each application, core0 calls rom_Boot(0x00014000, 0, 0, 0, 0x20210002, 0) to boot application of core0 and core1 also calls rom_Boot(0x00014000, 0, 0, 0, 0x20210002, 0) to boot application of core1. I programmed ldr file of ssl into default location in Flash (0x00000000) and press RESET : the ssl works OK (both cores OK). After I let the dual-core ssl to boot the dual-core application, the result is the following two situations:
If core0 boots first and core1 boots after, core0 boots successfully and works normal, but rom_Boot of core1 not been executed.
If core1 boots first and core0 boots after, core1 throws an exception:
//////////////////////////////////////////////////////////////////////////////////////////////////////
A non-recoverable error or exception has occurred.
Description: An instruction CPLB miss has occurred without a corresponding CPLB entry.
General Type: RunTimeError
Specific Type: ICPLBMissWithoutReplacement
Error PC: 0xffa00000
//////////////////////////////////////////////////////////////////////////////////////////////////////
after, core0 boots failure.
I checked several times and got the same result:
The L1 Instruction SRAM in core0 seems have been overwritten after core1 boot.
So I am surprise why the same file of dual-core works properly from default location but doesn't work from any other?
Why does only core0 run if the ssl is used to load the dual-core application?
Is the method of ssl booting the dual-core application not correct?
Where is the problem? Could anybody help me, please?
Thank you in advance
Williams
Hi,
I would suggest you to refer the EE-364 note for "How to write a SSL for ADSP-BF609 processors to selectively boot one of multiple executable files (DXEs) from SPI flash memory using basic GPIO push-buttons during system start-up". The example code provided in the associated .ZIP file, which has tested in ADSP-BF609 Ezkit.
www.analog.com/.../EE-364.pdf
www.analog.com/.../EE-364.zip
While looking into your query, you are trying to boot up the dual core BF609 application/project from the non default location using SSL where the each cores sharing a memory to each others.
Please find the below basic steps to use SSL to call the main application:
1) We would recommend you to create a single .ldr from the Dual core main application project with two .dxe's by using "-Nofinaltag" flag.
2) Load your main application .ldr to 0th sector and verify both the core's were running properly upon reset by using the various LED program into each core.
3) After verifying both the core's were working for your application, then you can load the application .ldr into any location.
4) Create a SSL project with Dual core and use the SSL calling function in the Core 0. You can have your additional codes or programs to run (Like sharing memory and LED) for the SSL project of the dual core should be executed before the calling SSL function.
Once the SSL function (ROM-API) is executed, the main dual core application is loaded into the first memory location in L1 instruction SRAM of the each core accordingly from the flash. Then, it performs whatever tasks it is intended to do, and it finally completes the boot process.(Mainly overwriting SSL application with the actual end application(main) which you stored in the FLASH's non default location.
Please note that the SSL would load the main application code into dual core's of the processor if the .ldr has dual core application. In this case, kindly make sure to Enable core 1 before calling the SSL, since this is required to load the core1's program from into core1 L1 instruction SRAM.
5) After, you can generate a single .ldr for the dual core SSL project and load it to 0th sector.
6) Upon Power up reset, the SSL will boot up your main application of dual core the ADSP-BF609 processor.
Regards,
Lalitha S
Hi, Lalitha
Thanks for your reply!
My problem has been solved owing to your detailed steps to boot a dual core application.
I modified two points in my dual core ssl and dual core application.
1) Combinning two ldr files of dual core application to a single ldr file, I only let core0 call rom_Boot function, not let core1 call rom_Boot function in ssl project.
2) Using adi_core_1_enable() instead of adi_core_enable(ADI_CORE_1) in main function of core0 in application project.
After doing this, the dual core ssl could boot the dual core application normally.
Thanks a lot again!
Regards,
Williams
Please log in to reply.