Adau1701 - Doubt about level input and sample rate
Hi folks...
I have two doubts about ADAU1701.
1. I wonder what the advantage in using an analog input level of 2VRMS instead of 0.9VRMS once that DAC full-scale level is 0.9VRMS.
2. The second doubt is about fs (input sampling rate). What is necessary for ADAU1701 working in 96KHz input sample rate? Even reading data sheet and another topics as https://ez.analog.com/dsp/sigmadsp/f/q-a/67283/adau1701-working-at-96khz I am confused.
On page 18 from data sheet we have the following statement "The oscillator is designed to work with a 256 × fS master clock, which is 12.288 MHz for a fS of 48 kHz and 11.2896 MHz for a fS of 44.1 kHz" and on topic above the following statement "The base sample rate of the device, which is used by the ADCs, DACs, and PLL, is called Fs. The ADAU1701’s design was based around the concept that Fs should equal either 48 kHz or 44.1 kHz".
With these statements I understand that ADAU1701 was designed to work with 48Khz or 44.1KHz, but sampling rates of up to 192 kHz are supported (according to data sheet).
For setup ADAU1701 with 96KHz input sample rate I can use a 24.576Mhz XTAL???
Thank you in advance.
Audio Signal Processors
SigmaDSP Audio Processors
adau1701
Hello Francis,
1. The ADAU1701's ADCs are current-sensing, so the external series resistors set their sensitivity. Just choose the resistor value that provides the desired full-scale input for your application. It works just as well with any of the choices in this table:
2. The short answer is, keep your 12.288 MHz crystal and "256xFs" PLL setting for 96K sample rate. Here's why:
Yes the data sheet's description of PLL settings, MCLK and sample rates is quite confusing. We can clear this up by considering how the -1701 runs its signal flow / program. The core is designed to work at up to 49.152 million instructions per second (MIPS). It must complete all the instructions on a given sample before the next one comes in. Thus at a sample rate of 48K, the core can handle 49152 / 48 = 1024 instructions. If you choose a 96K sample rate, the core cannot go any faster -- so your program can only use 49152 / 96 = 512 instructions. And at 192K, you only get 256 instructions to use. To handle the CD rate of 44.1K and its multiples, you would substitute a different crystal to slow the core clock to 45.1584 MIPS, and the number of instructions stays the same. Thus, the data sheet's Table 12 could be revised to make it more clear:
Bottom line: You always choose your hardware (crystal and PLL Mode) to set the MIPS clock to 49.1 MHz (or 45.1 MHz). The choice between 48/96/192K (or 44.1/88.2/176.4K) is done in SigmaStudio and amounts to a tradeoff between your sample rate vs. instruction limit.
The SigmaStudio sample rate must be set in two places -- Atop the schematic window:
And in the DSP Core (HW Config/1701 Register Control):
The two settings must agree with each other or else time-sensitive blocks like filters and oscillators will be off-frequency.
Now you can see that if you use a 24.576 MHz crystal with the same PLL settings as for a 12.288 MHz crystal, you're actually attempting 98.3 MIPS. That's overclocking your -1701 by a factor of 2. To run at 96K, set the schematic sample rate to 96K and your DSP core to "2X (512 Instructions)."
Best regards,
Bob
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