SC 58x TWI integration: TWI_MSTRSTAT.BUFRDERR problem

I am integrating drivers for the SPI on the SC589 eval board while our custom HW is being developed.

I'm starting by doing a simple register-write to an existing device.

I get the error condition on the master mode status register identified as bit 4, the BUFRDERR.

The documentation (Table 30-15 in the ADSP-SC58x ... SHARC+ Processor Hardware Reference) indicates that this is due to "detection of a NAK during data transmission."

However, neither the DNAK nor ANAK bits are set -- and doesn't the statement imply that I would see at least one of these?

Also, I observe the SCL and SDA on an oscope, and the sequence appears to be ACK'd appropriately.

I am also skeptical that the documentation for TWI_MSTRSTAT.BUFRDERR is correct, since the adjacent bit BUFWRERR has a quite different description. It makes sense, while this one doesn't (to me).