Downsample - Extract only odd / even samples
Hello!
I have the following problem.
I have an 96k input signal that I want to send it through a 48k domain. This means that I need to send
two packets of data in 48k domain. In order to do that, I need to use two channels and demux the data.
Ex:
96k Input channel 0: D1,D2,D3,D4....
48k Output
Channel 0: D1,D3,D5....
Channel 1: D2,D4,D6...
I was wontering if this is possible with SigmaDSP and Sigma studio.
Could I use an 96k Input channel and by using a demux with an 1-bit counter to "downsamle" the data into two streams of odd/even data?
The idea is to reconstruct the data on the other side of the link back to 96k..
Thanks in advance!
BR
downsample
demux
multiplex
SigmaDSP
Hello BR,
You can do some of these tricks. We have done some experiments with this in the past. Which SigmaDSP are you using?
So this data would simply be passed through with the possible exceptions of muting or something like that?
If you are passing through then almost nothing has to be done. Just send the input to the output. SigmaDSP would not need to know which sample is first and which sample is second.
We have done reconstruction as well. So it is possible.
I realized I need to edit this to add more detail.
If you are sending the data in I2S form where one sample is the first sample and the next 48kHz sample is the second 96kHZ sample will not work. You have to send four sample during every 48K sample period because you will need 4, 96kHz samples for every 48K sample period for stereo data. So if you are using two I2S lines then you will know which one has the earlier data so that is important.
If you can use TDM4 then you will stuff the data into specific slots so again you will know which is first.
I will use your sample rates as an example. The trick was this. We accessed the serial port at 96kHz rate but sent it data at a 48kHs rate. This means that the buffers had the same data for two sample periods in the core. The core was running at 96kHz. So now the core needs to know when to pick up the first sample and when to pick up the second sample. To do this we sent a 96kHz fs clock from the source device to a GPIO port. Then this GPIO was used to switch a MUX to select the first sample when it was low and the second when it was high. So that reconstructed the 96kHz data inside the core while transmitting it at 48kHz. The data had to be in TDM-4 or using two I2S ports.
We did this to receive 384kHz audio into the Sigma300 core even though the serial ports are limited to 192kHz fs. The core can run at 384kHz.
This works because the serial ports are simply shift registers and this value is only shifted into the data holding register at the end of the 48kHz frame. You can read the port data at any time, and multiple times, and if nothing changed because new data has not shifted in yet then the data stays the same.
I think I got all the details right. It was a year or so ago when we did this.
Dave T
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