EVAL ADAU1452 REV BZ StandAlone Mode
Dear Team,
Few queries related to on board AD1938 in ADAU1452 Rev BZ eval board .
1. The MCLK dictates the time for which the codec enters standalone mode which in my case is around ~ 5.23ms this time seems to be fairly impractical rendering it impossible to use the codec in developing environment since within this time frame I would not be able to configure the codec differently ,how do i then setup the codec in a different mode ?
2. It needs mention that the AD1938 in the board is set to standalone mode by group of resistors and by pulling the pins Cin CCLK Cout And Clatch low for a minimum of 5.23ms approximately
Now if i wanted to set the ADC as master without making any hardware changes (like removing the resistors or connecting te Cout to VCC) is it possible like pulling the Cout pin high in software ?
Again when the ADC is configured as slave and the serial port clock is also a slave then where does the ADC derive the clock from ?
Consider in standalone mode the Cout is tied low and all other pins cclk cin and Clatch are also tied low now the Serial port clock is configured as slave and the ADC clock pin is also a slave where does then the clock come from to the ADC?
Audio Signal Processors
adau1452
ad1938
Integrated/Special Purpose A/D Converters
SigmaDSP Audio Processors
Audio CODECs
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Hello Annihilate_123,
Let me take these one at a time.
1)
If you have a microcontroller, you need to place a pullup on the CLATCH line. Usually this pin is tied to a GPIO or to a pin on a controller that might be muxed with other functions so most parts the pin will power up in a high impedance mode or probably as an input. This means it will float high. This is usually enough to prevent the codec from going into standalone mode. Often the other pins are the same way, they will float high when powered up. So some care has to be taken to be certain that when initialized the pins will not all go low. The SPI latch pin (CLATCH) will initialize as high because it will not be trying to talk to any part right away. So I have not had anyone have any issue as long as they have the pull up resistor fitted.
The other small detail is that you have to be careful in your code that you do not have a long interrupt that might stop the SPI transaction in the middle of the transmission. It is possible that the clock and data will be low at the same time, the CLATCH is already low so if this conditions persists for the ~5.23 ms then it will enter standalone mode and be stuck there. So work your interrupts around this possibility. Again, I have not seen this be an issue very often with customers. The danger here is if you are not aware of this and you end up with a problem and no idea why it is happening.
2) The COUT Pin. When the part is in standalone mode. The COUT can be changed and it will change from master to slave. The pin is always active and will not latch into one or the other mode. So you could change this using a GPIO pin if desired. The other three pins once they are low for the required time, the part latches into the standalone mode and it does not matter what it going on with the CIN, CLK can CLATCH pins after that. So the COUT pin is not included in this timer for the standalone mode. Only the other three pins. COUT can be high or low and will always control the master/slave mode.
3) Clocks.
The part MUST have a master clock. In addition, the master clock MUST be correlated with the incoming LRCLK and BCLK. In other words, the part that is sending the data must have derived its clock from the same master clock. If the number of clock edges is incorrect then the part will mute. So the clocks for the ADC will be coming from the internal master clock and the serial port clocks will just be shifting in the data and signaling the start of the frame.
That said, this part does have a mode where the PLL can receive its clock from one of the LRCLK input pins. So it would slave to the incoming clock and not require a master clock. This mode can be tricky to use if high sample rates are used and if the clocks go away you have to restart the PLL. Should the clock shift suddenly then the PLL may lose lock and mute the output. So it is not the best way to clock the part but it can be done.
Dave T
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