ADAU1787-Upsample and Downsample of Fast Core and Sigma Core
Hi all,
I need to use ADAU1787 in low latency(A2A less than 100us) and low sample(12kHz)。In the Sigma Core or Fast Core, can I downsample the data of ADC from192k or 96k to 12kHz without filter, and can I upsample the data by zero order hold or zero insetion from 12kHz to192kHz or 96kHz without filter?
In the Sigma Core of ADAU1452, there are unsample module and downsample module。Does the ADAU1787 have the same module？
Thanks,
Audio Signal Processors
adau1452
ADAU1787
Integrated/Special Purpose A/D Converters
SigmaDSP Audio Processors
Audio CODECs
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Hello Zhou,
If the audio path in your application includes going down to 12kHz fs and back up it will use up most of the latency target you want. 12kHz fs is ~83us per sample. This is not counting any time for filters to change the sample rate. Then it will take one sample period to run the program in the SigmaDSP core so that will exceed your 100us allocation. I will check with the apps engineer for this part but I think there are some options for zero order hold but I want to check with you that you are not trying to get the 100us of latency with the audio being converted to 12kHz and back up to the higher fast core rate. Usually how this part is used is to have the audio path be only through the fast core. The audio is also passed to the SigmaDSP core at a lower rate to monitor the audio to then change filter coefficients of the filters in the fast core.
The part does have several asynchronous sample rate converters and synchronous sample rate converters for passing audio between the cores and between the serial ports and the cores. It is a very flexible part.
Dave T
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