ADAU1466 & Sigma Studio: Setting of Serial Inputs/outputs as Masters and Slaves; Clock Domains

Hello Patrick,

Mystic12 said:
In particular, what does Sigma Studio default to when using the input or output source symbols and can I change these clock domains manually with the hardware registers (it appears so) and then download and save to the eeprom, or is this incompatible with Sigma Studio?

I guess I need to step back and explain the very basics of what is going on. You will know some or all of this but I hope this will clear things up a bit.

SigmaStudio is used to compile and download the programs for the SigmaDSP products and it also is used to program the EEPROMs when needed. The other functions are to control the program objects running in the DSP while the program is running and then to be able to set up the registers in the part.

When the program is running you can also see most of the communications between SigmaStudio and the DSP in the Capture Window and you can see the parameters in the DSP memory in the Params Window. These tools serve to make it easy to see how the objects are controlled from an external device like a microcontroller. So the two basic modes of SigmaStudio is the Design Mode when you design the signal flow and the Active Download mode where SigmaStudio in just controlling the program running in the DSP. SigmaStudio never runs the program in the PC. These modes are visible on the far right bottom corner of the SigmaStudio window.

So when you look at the register windows these will be the settings that will be sent to the part when you program the part. If you do a "Read All" then SigmaStudio will read in all the register settings and display them on the screen. At that point SigmaStudio has the same settings as the DSP. However, use the Read-All VERY SPARINGLY. Because if you are using SPI and there is a communications problem, the data coming into SigmaStudio will be either all zeros or all ones. This will overwrite all the default register settings and there are over a hundred different registers in the part so this would be a mess to try to fix. So be certain to save your project before doing a Read-All unless you are using I2C.

In the SigmaStudio Schematic window you use it to control the data flow and calculations of the data in the DSP core. Just the core not the entire part. So you must use the registers to route the data into the core. Some times it is obvious like the serial ports that are hardwired into the core and sometimes the data needs to be routed like when you use the ASRCs. This part is quite complex so there are a lot of options and things going on in hardware around the DSP core.

The serial ports are explained in the datasheet and SigmaStudio does a decent job of showing these options in one place.

Clocking in this part is rather flexible and can do a lot so this makes it kind of complicated but there is no way around that. You need to be aware of the different types of serial data transmission and how they work. Then the settings are more clear. The serial ports can be a master. As a master the clocks come from inside the DSP and they are derived from the system clock which is the output of the PLL. The PLL is derived from the master clock input. The serial ports can also be slaves. So there are four serial input ports and four serial output ports. So therefore, you have four possible clock sources coming in for the serial input ports, and four possible clock sources coming into the serial output ports. Keep in mind that the name "serial input ports" or "serial output ports" refers to the direction of the serial data not the clocks. The clocks can be either direction. So you can send one set of clock to one of the serial input ports and then have all of the other three input ports slave off of that one clock input. No need to "Y" the clock signals externally. These are the serial clock domains 0 -3. The are the clock pins for serial ports 0 to 3. The same thing goes for the Serial Output ports. Note that there is not internal connection between the input and output port clock domains. These are separate and if you need them to be the same then that needs to be a "Y" externally. When any port is a master it uses the same internal clock source frequency selections as all the other ports. They cab be set to different internal frequencies but they are all derived from the same source.

Mystic12 said:
I have a precision 24.576mhz oscillator that is clocking a 1466. I use the clockout from this 1466 as the master for the ADC and the DAC. Also, I want to route one serial port output of the ADAU1466 to the serial port input of another ADAU1466 that is driven off of the same 24.576mhz master oscillator. have clkout on the first 1466 routed to the xtalin/mclk on the second ADAU1466 and both processors are running properly.

I think it is best to have your precision 24.576MHz clock feed both processor's MCLKIN pin. Yes, you can take the CLKOUT of the first 1466 an drive the second one but unless you need to shut down the other part into a very low power state by shutting off the clock, then I think it is best to simply distribute the same master clock to both parts. Then they will be running at the same rate and one is not dependent on the other for the master clock.

Mystic12 said:
I assume that I make the serial output port on the first ADAU1466 a master (both BCLK and LRCLK) and then make the serial port input on the second ADAA1466 a slave (both BCLK and LRCLK), but what clock domain should I use for the BCLK and LRCLK lines on this serial input port on the second ADAU1466? This is where the data sheet is a little sparse.

If you connect the BCLK and LRCLK on serial output port 0 of 1466#1 over to the BCLK and LRCLK serial input port 0 on 1466#2 then if 1466#1 is set to be a master then 1466#2 needs to be set to slave from clock domain 0 since those are the pins being used. Then you can connect the other SDATA pins to any of the other serial output ports to any of the serial input port pins and as long as you want the same serial format then you can slave all the serial input ports over to clock domain 0. If you want one to be I2S and another TDM then you have to send at least a different BCLK.

I should suggest you make all the serial output ports to be a master and all the serial input ports to be a slave as long as that works for your application. This will give you the best timing margins for reading the data properly when using high rates like 192kHz sampling rate or TDM formats with high bit clock rates.

Well, this is enough for now.

Thanks,

Dave T