ADAU1452 SPDIF receiver status bits
Hi,
I am currently using an ADAU1452, spdif receiver and trying to understand the "S/PDIF Receiver Channel Status Bits (Left) Register" as defined in the data sheet.
I am actually working on the design of an AES3 transmitter in VHDL so I am using the ADAU1452 as a "piece of test gear". My output is not being accepted as valid butI have another piece of equipment that does generate AES3 output, the ADAU1452 accepts it as valid so I want to compare it's Channel Status Bits to see where mine are wrong...
Most of the AES/EBU documents I have read talk about the 192 bit block in terms of "byte 0 bit 0" to byte 23 bit 7" where "byte 0 bit 0" is the first bit of the 192 bit block.
I have compared the received data to these documents and it would appear that the 192 bit block is stored as follows:
REG high byte low byte
F61B byte 1 byte 0
F61A byte 3 byte 2
F619 byte 5 byte 4
...
F610 byte 23 byte 22
This is what I have actually read:
SR Bits Channel Status registers (F610 to F61B)
44.1 16 : 6b00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0008 8245
48 16 : 2e00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0008 8285
88.2 16 : 8000 0000 0000 0000 0000 0000 0000 0000 0000 0050 0008 8205
96 16 : c900 0000 0000 0000 0000 0000 0000 0000 0000 0010 0008 8205
44.1 20 : 8000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0028 8245
48 20 : c500 0000 0000 0000 0000 0000 0000 0000 0000 0000 0028 8285
88.2 20 : 6b00 0000 0000 0000 0000 0000 0000 0000 0000 0050 0028 8205
96 20 : 2200 0000 0000 0000 0000 0000 0000 0000 0000 0010 0028 8205
44.1 24 : ef00 0000 0000 0000 0000 0000 0000 0000 0000 0000 002c 8245
48 24 : aa00 0000 0000 0000 0000 0000 0000 0000 0000 0000 002c 8285
88.2 24 : 0400 0000 0000 0000 0000 0000 0000 0000 0000 0050 002c 8205
96 24 : 4d00 0000 0000 0000 0000 0000 0000 0000 0000 0010 002c 8205
I logically expected byte 0/1 to be in register F610 and so on up so this has confused me.
Could anybody confirm that this is the correct and expected order ?
Many Thanks in anticipation
PhilipJ
Audio Signal Processors
adau1452
SigmaDSP Audio Processors
Hello Phillip,
I am afraid I do not have too much info that can help. This detail is not covered in the datasheet and I looked into the design notes internally and did not see a discussion about it. What I suspect is that the registers are internally setup to take the contents of a shift register that is used to shift in the bits one sample period at a time. So this register will be 192 bits long with the first bit received being at the end of the 192 bit shift register. So then when this shift register is transferred to the 12, 16 bit registers, it will end up with the first bits at the end. So I am guessing this is what is happening. It would have to get a design engineer off of a current project to open up this design and see id this is indeed what is happening and that is difficult to do right now.
By the way, I knew this and also ran across it again in my search. The SPDIF receiver does not decode any of the channel status and user data information with the exception of the word-length and compression status information. So for example, if the validity bit is set to show invalid data we will ignore it and continue to process the audio. This is why the ADAU1452 will accept almost anything as valid data. Of course the block structure needs to be good and the signal valid so the PLL can lock to it.
Dave T
Hi Dave, thanks for checking. I later found that the problem I was having was because the transmitter was incorrectly generating the Parity bit on some, not all, frames. This caused the receiver to drop in and out of lock. Not checking the Channel Status bits is actually a help because it means we can add to our product, a simple AES3 input analyser.
regards
PhilipJ
Please log in to reply.