ADAU1701 Delay between MCLK and BCLK/LRCLK when used as a slave device
We plan to use the ADAU1701 as a slave device.
Have MCLK, BCLK, LRCLK supplied from the master side
datasheet P48 has the following description "The serial data clocks need to be synchronous with the ADAU1701 master clock input. "
What is the allowable delay amount for MCLK and BCLK/LRCLK?
Audio Signal Processors
SigmaDSP Audio Processors
adau1701
Hello UBOTI,
The edges of the MCLK clock to the BCLK/LRCLK does not matter. What matters is that they are exactly in sync in that if you are set to an MCLK of 256 x fs then there needs to be exactly 256 master clock edges in each frame. No more no less.
To do this means that they usually are all derived from the same clock source so there will be no drift.
Dave T
Thank you for your answer
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