ADSP-214xx SPORT DMA Index Register

ADSP-214xx SHARC Processor Hardware Reference, page 3-4 mentions about Index registers as follows.

"All internal index registers have 18-bit address width. However all index registers are based on an internal memory offset of 0x80000 (bit 19 set) so the total width results to 19 bits. This internal memory offset is not applicable for the index registers that correspond to SPORT DMAs as these registers are 28 bits".

Suppose I have a data buffer for SPORT0 DMA on internal DM. Then, I need 0x80000 offset be subtracted to IISP0 (like Examples in VDSP++ installation does)? Or, to IISP0 register in 28bit width, address offset 0x80000 no longer requried?

If data buffer is on external memory, then 0x80000 offset is still required?

I'm confused with 28bit extension to SPORT Index registers. When address offset 0x8000 is still taken into account for SPORT index registers ?

e.g., )

unsigned int my_buffer[512];

void my_sport0_dma_init()

{

...

*pIISP0 = (int) my_buffer; // without 0x8000 offset to SPORT index register?

// OR ?

*pIISP0 = (int) my_buffer - 0x80000; // OR, need this only when my_buffer is on internal memory ?

}

Thank you for your support.