Accelerator Chain Pointer Register (specifically FIR)

Hello,

I am still learning all the peculiarities of the SHARC processor. I am stumped trying to get the hardware accelerators to work.

Based on my understanding of the documentation, you create a TCB in memory. Then you load the address of this TCB in to the chain pointer register. The accelerator then fills all of it's DMA registers (IBMLC, etc) based on the values in said TCB.

So I have gone ahead and done all that. Unfortunately when I load the chain pointer address into the CPFIR register, the address gets mangled. It appears that it masks everything from bit 19 onward. This means I can only feed it addresses 7FFF or lower. Unfortunately my addressing doesn't go that low.

If I am required to change this (if it is even possible?) please let me know how I may go about doing this. As far as I am aware though, I have a default set up, and in the documents there was no mention of needing to mess around with memory addressing to get this to work.

I figure I am either missing a crucial piece of the puzzle here, or these hardware accelerators have a fatal design flaw. The latter is probably more likely.

I would greatly appreciate some support.

Thank you