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adau1452 ASRC can it work on 32-bit audio

SigmaDSP & SigmaStudio philipj451 Oct 12, 2020 00:00 3 replies Original on forum ↗
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philipj451 Question
Oct 12, 2020 00:00

Hi,

I am working on a system design that supplies 4 audio streams to an ADAU1452 from 4 different "clock" domains. Each stream will be fed into the ADAU1452 via one of it's SDATA inputs which will be working in the Raw 32-bit mode.

Because the 4 clock domains are not synchronised then each will need to go through an ASRC so my questions are:

1) Do the ASRCs work OK with 32-bit data?

2) To make the SDATA ports work in the Raw 32-bit mode it seems I should include them in my Schematic design but turn all the 'ticks' off i.e.

and use the Hardware Configuration -> Routing Matrix Tab to connect the input channels to the ASRCs

is this correct?

Thanks for any advice

PhilipJ

Audio Signal Processors

adau1452

SigmaDSP Audio Processors

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DaveThib Reply
Oct 12, 2020 00:00

Hello PhilipJ

1) Unfortunately, the ASRCs are only 24 bit. They are in hardware so there is no way to change this. Are all the sources 32 bit? If only one of them is 32 bit then you can set that input synchronized to the core and then the others can use the ASRCs.

2) If you are using the ASRCs then you do not even need the input block at all. You will be using the ASRC input block and like you mentioned, the ASRC inputs will be set to the serial ports and this happens before the signal ever reaches the core. So this is why you do not need the input blocks.

But, it is 24 bits.

Dave T

philipj451 Reply
Oct 16, 2020 00:00

Hi Dave,

unfortunately all the four streams are potentially 32-bit. I have done what you suggest, the DSP is synchronous with the first of the 4 streams so it doesn't need an ASRC but the other 3 aredifferent clock domains.

My reason for using 32-bit is that each stream comes from a Dante bus which has up to 64 channels that may be "mixed" into a stereo LR signal (done in an FPGA). It's possible the mix could overflow the maximum 24-bits so I thought the easiest way to deal with it was pass the streams to the SigmaDSP as 32-bit, add the 4 streams together and then put a limiter block on the output signal before feeding it to DACs via I2S output streams.

I guess I'm going to have to learn how to do the limiter function in the FPGA!!

thanks for your advice

PhilipJ

Raph Reply
May 3, 2021 00:00

Hi Dave,

Does this limitation to 24bits of the hardware ASRC exist on the ADAU1462 as well ?

Thank you.