What is the "power-down" state of the ADAU145x?

Bump... seems like a datasheet omission.

Hello Joe,

Let me try to answer some of this for you. The IOVDD is mostly left out because it is so dependent on external conditions that make writing specs too difficult for a part like this with many bi-directional serial ports. It is very dependent on user configuration. You are correct that you should not gate the IOVDD voltage.

Reset does draw a lot of current so I would not keep the part in reset for extended periods of time.

Hibernation is a rather simple state where all the interrupts for the core are disabled. This means that the program never starts running since it is waiting for the start of frame ( Start Pulse ) interrupt. So since the DVDD current is the predominate current at room temperature this will keep current draw low for DVDD.

The best way to place it into a low power state would be to stop the core and put it into hibernation, then shutdown the power enable registers to power down sections of the part. We did not take these measurements for the datasheet unfortunately.

There is another way, just stop the master clock and that will simply stop everything in the part. The power down registers simply stop the clocks to those sections so stopping the master clock will lower the power draw. The downside is you have to wait for the PLL to relock and then there may be some clicks or pops when stopping and restarted. So that is easily solved by muting before you shut down the part.

Another thing you can do is to disable the PLL. This will lower the system clock from the ~294MHz down to the rate of the crystal which is usually 12.228MHz. So the part is still running but really slowly. You can mute the audio and stop the core before doing this.

Do you have an evaluation board? If you do then which one?

Dave T

Thanks for the response! I'll implement whatever suggestion is "best practice", which sounds like putting the core into hibernation and shutting down the power enable registers. It's unfortunate (and surprising) this isn't well documented, as it's very important for standby power compliance.

These all sound like decent options and it's nice none of them require removing IOVDD though. Since I'm currently doing the hardware side, it seems that I can confidently omit power switches for AVDD, IOVDD, and DVDD, and just rely on software?

I have a ADAU1452MINIZ for evaluation, but am implementing on ADAU1451 (which should be the same for these purposes).

Hello Joe42,

The power dissipation difference between the 1452 and the 1451 will be small.

You can remove R23 and insert a current meter to measure the DVDD current but there are no other parts to remove to make measuring the current usage of just the DSP on the other power supplies. I thought we had that in the design but it does not have that ability. I was not involved in the design of this particular eval board.

Yes, I would rely on software. It is best not to gate the power and it is not a good idea to drop the IOVDD alone. It will not damage the part but it leaves it more susceptible to ESD damage and if any signal lines are high, or have clocks on them, when the IOVDD is down will cause a condition where the max voltage on the pins is exceeded.

Dave T

OK, as long as I can be confident software shutdowns will be sufficient (seems to be from your description) then I will forego hardware shutdowns.

(I learned the hard way years ago destroying a few 1701 chips that still had I2C active and no power applied. Oops!)

Hello Dave,

I was about to post exactly the same question when I stumbled on this thread.

May I add another question to it? (i hope for a 'yes' so I will continue): Is it OK to stop the master clock AND put the device in reset for a longer period of time to save power? The datasheet does mention the reset currents drawn by the AVDD and PVDD and a power down current for the IOVDD. So my intention was to reset the chip AND disabling the master clock at the same time to save power. Would that be a valid way?

With kind regards,

Reini

Hello Reini,

Great to hear from you. It has been a while.

I actually would not recommend keeping it in reset for long periods of time. The part does a strange thing where it draws more current in reset than it does when running a smaller program. Since I posted this I also found that in hibernation it also draws slightly more than when it is just not running a program. So changing the start pulse to something that has no signal will just stop the core and it will perform no-ops and draw less power. At this point it has been too long from when this part was designed for me to get good answers about this from the designers. Anyhow, on to your specific questions.

I would just stop the MCLK. That will stop everything and the advantage is that when you resume sending it MCLK it will just start from where it left off and you will not have to reprogram the part. All the registers will hold their settings etc. That is an advantage. So that is my suggestion.

Dave T

Hello Dave,

Thanks for the answer! I already changed my design to be able to stop the master clock :-) So that's what I'm going to test on the prototype. I also did some measurements on another prototype where the clock was stopped and the chip indeed seems to draw very little current when it is not clocked.

So I now only need to change my firmware where the DSP is being shutdown (not resetting, just stopping the MCLK).

Thanks again for responding :-)

With kind regards,

Reini