DC offset in ADC - minimize/characterize? (ADAU1701)

I noticed a nontrivial DC offset present in the audio ADC that's causing some problems, particularly when low inputs are present (say, 100mVpp) from the customer device, and a fair bit of gain is applied. Hardware interface is fairly conventional, with a 10uF blocking cap.

Shorting the ADC input to CM (making it zero), and feeding this result to the DAC directly shows about 40mV offset. (This may include a DAC offset if it exists). This is quite a surprisingly high number, basically 2.7% of full scale, making it quite a number of bits on a 24-bit ADC. Is this typical? I note that it's not mentioned in the datasheet, though 15mV offset is specified for the AUX ADC.

Obviously I can add a DC blocking block to my schematic, but I'd rather avoid this if possible. This project calls for 192kHz sample rate, and every cycle is precious.

I was hoping that there was a hidden register or something for the ADC itself, as there is with other parts, or perhaps there is a hardware cure to reduce this?

Audio Signal Processors

SigmaDSP Audio Processors

adau1701 adc

adau1701