ADAU1452 Random Clock Phase on Startuyp

I'm running the ADAU1452 with a 192k sample rate. I have I2S input from a source at 24k. All clocks are running from the same external source, and I'm using direct input, no ASRCs involved.

The 24k data gets upsampled in an upsampling block.

What I am seeing is that the data gets delayed by a number of 192k samples ranging from 0 to 7 samples on a random basis. This latency changes each time the chip is reloaded and restarted.

I'm assuming this is happening because the 24k clock is coming up in a random phase relationship.

Is there any way to make the 24k clock come up deterministically?

Thanks,

-PolEx

Audio Signal Processors

adau1452

SigmaDSP Audio Processors