I2C master read data from sense registers
Hi,
as said in the previous conversation, I have made the necessary settings in control register (0x06) with data (10000100) and when i try to read data from register (0x00) it is just giving out (0x0000).
i have put the snapshot of what is been observed in the logic analyzer.
I would like to know even though doing necessary settings, the register is not reading proper data instead giving out (0x0000).
why is this happening?
Iam attaching my vhdl code also for your reference so that you could guide me on where iam doing wronglibrary IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity i2c_2 is
generic( system_frequency : integer := 64000000; --expressing 64MHz in hertz
req_freq : integer := 400000 --enter input in Hertz (400kHz) for better precision
);
port ( CLK : IN std_logic;
RST_N : IN std_logic;
SCL : OUT std_logic;
SDA : INOUT std_logic;
iscl_clk : OUT std_logic;
flag_ch : OUT std_logic
);
end i2c_2;
architecture behav of i2c_2 is
constant slaveaddr_w : std_logic_vector (7 downto 0) := "11011110"; --xDE --slave address + write
constant slaveaddr_r : std_logic_vector (7 downto 0) := "11011111"; --xDF --slave address + read
constant control_reg : std_logic_vector (7 downto 0) := "00000110"; --x06 --address of control reg
constant control_data: std_logic_vector (7 downto 0) := "10010100"; --Data to be written to slave's control reg
constant reg1 : std_logic_vector (7 downto 0) := "00000000";
signal reg1_data: std_logic_vector (7 downto 0);
signal reg2_data: std_logic_vector (7 downto 0);
signal tmp_clk : std_logic;
signal scl_clk : std_logic;
signal scl_int : std_logic := '1';
signal sda_int : std_logic := '1';
signal bit_cnt : integer := 7;
signal state : integer := 0;
signal slave_ack : std_logic; --slave acknowledgement
signal data_out: std_logic_vector (7 downto 0); --Data to be read from slave
begin
process (RST_N,CLK)
variable counter : integer := 0;
variable count : integer := ((system_frequency/req_freq)/2) - 1;
begin
if (RST_N = '0') then --reset asserted
tmp_clk <= '0'; --initializing temporary signal to zero.
counter := 0; --counter initialised to zero
count :=((system_frequency/req_freq)/2) - 1; --formula to convert the frequency to count.
elsif (rising_edge(CLK)) then --Divide by 2 is to maintain 50% duty cycle
if (counter = count) then
tmp_clk <= not(tmp_clk);
counter := 0;
else
counter := counter + 1; --increment the counter
tmp_clk <= tmp_clk;
end if;
end if;
end process;
scl_clk <= tmp_clk;
iscl_clk <= scl_clk;
process (RST_N, scl_clk)
begin
if (RST_N = '0') then
scl_int <= '1';
sda_int <= '1';
elsif (rising_edge (scl_clk)) then
case state is
when 0 => --idle
scl_int <= '1';
sda_int <= '1';
state <= 1;
when 1 => --start
scl_int <= '1';
sda_int <= '0';
bit_cnt <= 7;
state <= 31;
when 31 =>
scl_int <= '0';
sda_int <= '0';
bit_cnt <= 7;
state <= 2;
---------------------------------------------------
when 2 => --load slave address with write
scl_int <= '0';
sda_int <= slaveaddr_w(bit_cnt);
state <= 3;
when 3 =>
scl_int <= '1';
if (bit_cnt > 0) then
bit_cnt <= bit_cnt - 1;
state <= 2;
elsif (bit_cnt = 0) then
bit_cnt <= 7;
state <= 4;
end if;
---------------------------------------------------
when 4 => --slave acknowledge bit
scl_int <= '0';
state <= 5;
when 5 =>
scl_int <= '1';
slave_ack <= SDA;
if (SDA = '1') then
state <= 2;
elsif (SDA = '0') then
state <= 6;
end if;
---------------------------------------------------
when 6 => --load control reg address
scl_int <= '0';
sda_int <= control_reg (bit_cnt);
state <= 7;
when 7 =>
scl_int <= '1';
if(bit_cnt > 0) then
bit_cnt <= bit_cnt - 1;
state <= 6;
elsif (bit_cnt = 0) then
bit_cnt <= 7;
state <= 8;
end if;
---------------------------------------------------
when 8 => --slave acknowledge bit
scl_int <= '0';
state <= 9;
when 9 =>
scl_int <= '1';
slave_ack <= SDA;
if (SDA = '1') then
state <= 6;
elsif (SDA = '0') then
state <= 10;
end if;
---------------------------------------------------
when 10 => --load control reg data
scl_int <= '0';
sda_int <= control_data (bit_cnt);
state <= 11;
when 11 =>
scl_int <= '1';
if (bit_cnt > 0) then
bit_cnt <= bit_cnt - 1;
state <= 10;
elsif (bit_cnt = 0) then
bit_cnt <= 7;
state <= 12;
end if;
---------------------------------------------------
when 12 => --slave acknowledge bit
scl_int <= '0';
state <= 13;
when 13 =>
scl_int <= '1';
slave_ack <= SDA;
if (SDA = '1') then
state <= 10;
elsif (SDA = '0') then
state <= 14;
end if;
---------------------------------------------------
when 14 => --stop
scl_int <= '0';
sda_int <= '0';
state <= 15;
when 15 =>
scl_int <= '1';
sda_int <= '0';
state <= 16;
when 16 =>
scl_int <= '1';
sda_int <= '1';
state <= 18;
----------------------------------------------------------------------------------------------------
-----start op-----
-- when 17 =>
-- scl_int <= '1';
-- sda_int <= '1';
-- state <= 18;
when 18 => --start
scl_int <= '1';
sda_int <= '0';
state <= 19;
---------------------------------------------------
when 19 =>
scl_int <= '0'; --load slave address with write
sda_int <= slaveaddr_w(bit_cnt);
state <= 20;
when 20 =>
scl_int <= '1';
if (bit_cnt > 0) then
bit_cnt <= bit_cnt - 1;
state <= 19;
elsif (bit_cnt = 0) then
bit_cnt <= 7;
state <= 21;
end if;
---------------------------------------------------
when 21 => --slave acknowledge
scl_int <= '0';
state <= 22;
when 22 =>
scl_int <= '1';
slave_ack <= SDA;
if (SDA = '1') then
state <= 19;
elsif (SDA = '0') then
state <= 41;
end if;
---------------------------------------------------
when 41 => -- load control register address
scl_int <= '0';
sda_int <= control_reg (bit_cnt);
state <= 42;
when 42 =>
scl_int <= '1';
if (bit_cnt > 0) then
bit_cnt <= bit_cnt - 1;
state <= 41;
elsif (bit_cnt = 0) then
bit_cnt <= 7;
state <= 43;
end if;
---------------------------------------------------
when 43 => -- slave acknowledge
scl_int <= '0';
state <= 44;
when 44 =>
scl_int <= '1';
slave_ack <= SDA;
if (SDA = '1') then
state <= 41;
elsif (SDA = '0') then
state <= 45;
end if;
---------------------------------------------------
when 45 => -- restart
scl_int <= '0';
sda_int <= '0';
state <= 46;
when 46 =>
scl_int <= '0';
sda_int <= '1';
state <= 47;
when 47 =>
scl_int <= '1';
sda_int <= '1';
state <= 48;
when 48 =>
scl_int <= '1';
sda_int <= '0';
state <= 49;
when 49 =>
scl_int <= '0';
sda_int <= '0';
state <= 50;
---------------------------------------------------
when 50 => --load slave address with read
scl_int <= '0';
sda_int <= slaveaddr_r (bit_cnt);
state <= 51;
when 51 =>
scl_int <= '1';
if (bit_cnt > 0) then
bit_cnt <= bit_cnt - 1;
state <= 50;
elsif (bit_cnt = 0) then
bit_cnt <= 7;
state <= 52;
end if;
---------------------------------------------------
when 52 => --slave acknowledge
scl_int <= '0';
state <= 53;
when 53 =>
scl_int <= '1';
slave_ack <= SDA;
if (slave_ack = '1') then
state <= 50;
elsif (slave_ack ='0') then
state <= 37;
end if;
---------------------------------------------------
when 37 => --read data from slave
scl_int <= '0';
state <= 38;
flag_ch <= '1';
when 38 =>
scl_int <= '1';
flag_ch <= '1';
if (bit_cnt > 0) then
data_out(bit_cnt) <= SDA;
bit_cnt <= bit_cnt - 1;
state <= 37;
elsif (bit_cnt = 0) then
data_out(bit_cnt) <= SDA;
bit_cnt <= 7;
state <= 34;
end if;
---------------------------------------------------
-- when 29 => --master NACK
-- scl_int <= '0';
-- sda_int <= '0';
-- state <= 30;
--
-- when 30 =>
-- scl_int <= '1';
-- sda_int <= '1';
-- state <= 34;
---------------------------------------------------
when 34 => --stop
flag_ch <= '0';
scl_int <= '0';
sda_int <= '0';
state <= 35;
when 35 =>
scl_int <= '1';
sda_int <= '0';
state <= 36;
when 36 =>
scl_int <= '1';
sda_int <= '1';
flag_ch <= '1';
state <= 70;
---------------------------------------------------
when 70 => --start
scl_int <= '1';
sda_int <= '0';
state <= 71;
---------------------------------------------------
when 71 =>
scl_int <= '0'; --load slave address with write
sda_int <= slaveaddr_w(bit_cnt);
state <= 72;
when 72 =>
scl_int <= '1';
if (bit_cnt > 0) then
bit_cnt <= bit_cnt - 1;
state <= 71;
elsif (bit_cnt = 0) then
bit_cnt <= 7;
state <= 73;
end if;
---------------------------------------------------
when 73 => --slave acknowledge
scl_int <= '0';
state <= 74;
when 74 =>
scl_int <= '1';
slave_ack <= SDA;
if (SDA = '1') then
state <= 71;
elsif (SDA = '0') then
state <= 75;
end if;
---------------------------------------------------
when 75 => -- load register1 address
scl_int <= '0';
sda_int <= reg1 (bit_cnt);
state <= 76;
when 76 =>
scl_int <= '1';
if (bit_cnt > 0) then
bit_cnt <= bit_cnt - 1;
state <= 75;
elsif (bit_cnt = 0) then
bit_cnt <= 7;
state <= 77;
end if;
---------------------------------------------------
when 77 => -- slave acknowledge
scl_int <= '0';
state <= 78;
when 78 =>
scl_int <= '1';
slave_ack <= SDA;
if (SDA = '1') then
state <= 75;
elsif (SDA = '0') then
state <= 79;
end if;
---------------------------------------------------
when 79 => -- restart
scl_int <= '0';
sda_int <= '0';
state <= 80;
when 80 =>
scl_int <= '0';
sda_int <= '1';
state <= 81;
when 81 =>
scl_int <= '1';
sda_int <= '1';
state <= 82;
when 82 =>
scl_int <= '1';
sda_int <= '0';
state <= 83;
when 83 =>
scl_int <= '0';
sda_int <= '0';
state <= 84;
---------------------------------------------------
when 84 => --load slave address with read
scl_int <= '0';
sda_int <= slaveaddr_r (bit_cnt);
state <= 85;
when 85 =>
scl_int <= '1';
if (bit_cnt > 0) then
bit_cnt <= bit_cnt - 1;
state <= 84;
elsif (bit_cnt = 0) then
bit_cnt <= 7;
state <= 86;
end if;
---------------------------------------------------
when 86 => --slave acknowledge
scl_int <= '0';
state <= 87;
when 87 =>
scl_int <= '1';
slave_ack <= SDA;
if (slave_ack = '1') then
state <= 84;
elsif (slave_ack ='0') then
state <= 88;
end if;
---------------------------------------------------
when 88 => --read data from slave
scl_int <= '0';
state <= 89;
flag_ch <= '1';
when 89 =>
scl_int <= '1';
flag_ch <= '1';
if (bit_cnt > 0) then
reg1_data(bit_cnt) <= SDA;
bit_cnt <= bit_cnt - 1;
state <= 88;
elsif (bit_cnt = 0) then
reg1_data(bit_cnt) <= SDA;
bit_cnt <= 7;
state <= 90;
end if;
---------------------------------------------------
when 90 => --master ACK
scl_int <= '0';
sda_int <= '0';
state <= 91;
when 91 =>
scl_int <= '1';
sda_int <= '0';
state <= 92;
---------------------------------------------------
when 92 => --read data from slave
scl_int <= '0';
state <= 93;
when 93 =>
scl_int <= '1';
if (bit_cnt > 0) then
reg2_data(bit_cnt) <= SDA;
bit_cnt <= bit_cnt - 1;
state <= 92;
elsif (bit_cnt = 0) then
reg2_data(bit_cnt) <= SDA;
bit_cnt <= 7;
state <= 94;
end if;
---------------------------------------------------
when 94 => --master NACK
scl_int <= '0';
sda_int <= '0';
state <= 95;
when 95 =>
scl_int <= '1';
sda_int <= '1';
state <= 96;
---------------------------------------------------
when 96 => --stop
flag_ch <= '0';
scl_int <= '0';
sda_int <= '0';
state <= 97;
when 97 =>
scl_int <= '1';
sda_int <= '0';
state <= 98;
when 98 =>
scl_int <= '1';
sda_int <= '1';
flag_ch <= '1';
state <= 98;
---------------------------------------------------
when others => --idle
scl_int <= '1';
sda_int <= '1';
state <= 0;
end case;
end if;
end process;
SCL <= '0' when scl_int = '0' else '1';
SDA <= '1' when sda_int = '1' else '0';
end behav;
Please help me resolve the issue .
Thank You
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