Problem of core timer of BF533
Hi.
I am using BF533 in a project .
crystal oscillator clok = 24.576MHz
Set PLL at 20x. Core clock=24.576*20=491.5MHz
SCLK=491.5/2=245.76MHz
The DMA1 interrupt runs at 192KHz by SPORT0 ,DMA5 interrupt runs at 192KHz too.
192KHz I2S data in from SPORT0 and output via DMA5 by SPI0 .
Now i need to add a 384K pulse , I used core timer to generate this pulse.
EX_INTERRUPT_HANDLER(CORE_TIMER_ISR)
{
*pTCNTL = *pTCNTL & 0xFFF7; // reset TINT (interrupt bit)
*pFIO_FLAG_D |= PF4;
*pFIO_FLAG_D &= ~PF4;
}
void Init_Core_Timer(void)
{
*pTCNTL = 0x0007; // enables the timer and sets it to auto reload
*pTPERIOD = 640;
*pTCOUNT = 640;
*pTSCALE = 1;
}
register_handler(ik_timer, CORE_TIMER_ISR);
*pIMASK|=0x00000020;
But, I can not get the right pulse . The pulse is disordered .
When i set *pTPERIOD = *pTCOUNT = 24576; i can get 10KHz pulse .
When i set *pTPERIOD = *pTCOUNT = 2458; i can get 100KHz pulse .
I can not get pulse over 192KHz, when *pTPERIOD ( *pTCOUNT) less than 1280, the pulse will disordered .
The interrupt of core timer should have high priority, it should not be affected by DMA interrupt .
Can anybody help me ?
ADD *pIMASK|=0x00000020;
[edited by: Xuzhengyu at 8:44 AM (GMT -5) on 18 Feb 2021]
Hi,
Please note that the maximum SCLK is 133Mhz. We suggest to maintain the limitation as mentioned in the ADSP-BF533 datasheet under Table 13. System Clock (SCLK) Requirements (PageNo:21/64). We cannot guarantee the proper operation of the devices if the customer is not following the clock specification.
We suggest you to refer the Table 13. System Clock (SCLK) Requirements (PageNo:21/64) section datasheet of ADSP-BF533. You can refer the datasheet from below link,
www.analog.com/.../ADSP-BF531_BF532_BF533.pdf
Please refer the Core Clock/System Clock Ratio Control (PageNo:329/884) section in the HRM of ADSP-BF533. You ca refer the HRM from below link,
www.analog.com/.../ADSP-BF533_hwr_rev3.6.pdf
Regards,
Anand Selvaraj.
Thanks.
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