How to use the SPORT controller (register setting)
Hi,
Using the SPORT controller,
Audio-digital serial communication with an external CODEC IC is performed (I2S format).
The SPORT controller can select which clock edge to sample the transmitted / received data at the following registers.
・ RCKFE bit of RCR1 (primary reception configuration register)
RCKFE = 0 Drive at the rising edge of RSCLK, sample at the falling edge
RCKFE = 1 Drive at the falling edge of RSCLK, sample at the rising edge
・ TCKFE bit of TCR1 (primary transmission configuration register)
TCKFE = 0 Drive at the rising edge of TSCLK, sample at the falling edge
TCKFE = 1 Drive at the falling edge of TSCLK, sample at the rising edge
This time, this bit is (not RCKFE = TCKFE)
RCKFE = 0, TCKFE = 1
I would like to set it to, but is there any problem?
ADSP-BF537 Blackfin Processor Hardware Reference
Looking at pages 12-36,
The transmit and receive functions of two SPORTs connected together should always select the same value for TCKFE in the transmitter and RCKFE in the receiver, so that the transmitter drives the data on one edge and the receiver samples the data on the opposite edge.
There is a description that
As a specification of Blackfin, I would like to know if it is necessary to have RCKFE = TCKFE.
Best Regards,
Naohisa
Audio Signal Processors
adsp-bf537
Blackfin Embedded Processors
Hi Naohisa,
As given in HRM, the transmitter will drive the data on one edge and receiver will sample the data on the opposite edge. When TCKFE=1 and RCKFE=0, data and internally generated Frame sync is driven on the falling edge and sample at the falling edge which is not possible. Hence, I would suggest you to follow the descriptions/specifications available in the HRM failing to do so may result in erroneous output.
Regards,
Anand Selvaraj.
Hi Anand,
The following registers of SPORT were originally set as follows.
◆ SPORTx Transmit Configuration 1 Register (SPORTx_TCR1)
TCKFE = 1: Drive data and internal frame syncs with falling edge of TSCLK.
Sample external frame syncs with rising edge of TSCLK.
ITCLK = 1: Internal transmit clock selected
ITFS = 1: Internal TFS used
◆ SPORTx Receive Configuration 1 Register (SPORTx_RCR1)
RCKFE = 1: Drive internal frame sync on falling edge of RSCLK.
Sample data and external frame sync with rising edge of RSCLK.
IRCLK = 0: External receive clock selected
IRFS = 0: External RFS used
In other words, the transmitter clock is generated inside the DSP and output.
The receiving clock is input by wrapping the transmitting clock externally.
In this case, TSCLK and RSCLK are the same clock source,
It is a recognition that it is treated as another clock and does not need to be synchronized.
This time, the output delay of SDTO (DOUT) of the alternative CODEC is large,
I'm not satisfied with the Blackfin setup time.
Therefore, as shown in the figure below, we are trying to delay RFS and DRxPRI by half a clock with D-FF.
As a result, I am trying to change RCKFE from 0 to 1.
At the time of using separate clocks for the transmitter and receiver
I think that RCKFE ≠ TCKFE is possible, but how about it?
Best Regards,
Naohisa
Hi.
Could you answer this question?
I'm in trouble and want help.
Best Regards,
Naohisa
Hi.
Could you answer this question?
I'm in trouble and want help.
Best Regards,
Naohisa
Hi Naohisa,
Apologies for the delayed response.
Looking at the figure you have shared, it looks like transmitter generates the clock/frame sync and fed to receiver and CODEC. If this was the case, as already mentioned it is necessary to set both TCKFE and RCKFE bits to same value. This is to ensure that sample and drive edges are opposite. As long as this is taken care, there should be no issue.
Regards,
Anand Selvaraj.
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