ADAU1979: What starts a conversion cycle?
We're using multiple ADAU1979 ADC's in our design. The datasheet for this ADC is notably vague on which clocks are controlling the internal conversion. It is understood that the LRCLK and BCLK control the output data transfer. It is implied that the MCLKIN controls internal processes, but I can't find anything that mentions what impetus triggers a conversion cycle.
Why I'm asking: We need to synchronize the conversion across all of our ADC's, and when I say synchronize, I'm not referring to the output data transfer. I need all ADC's to be STARTING their conversion cycles at precisely the same moment in time. We're currently seeing variation from boot to boot, which we suspect is due to variance in PLL lock times. Certainly we can watch all the PLL lock bits to make sure everything is up, but how do I make sure none of the ADCs start sampling/converting before they're all ready?
A follow-on question: Is the PLL lock subject to the reset (~PD/~RST) pin? That is, will the PLL acquire lock if MCLKIN is provided BEFORE the chip is pulled out of reset?
Does anyone have any thoughts? Perhaps there's an undocumented register that stops (or resets) the conversion process...?
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