ADAU Fast & Sigma clock frequencies
Now then. I need to run the Fast core at 768KHz for reasons of latency, but can run the S core at 24 or 32KHz (48KHz won't work as not enough cycles available). The problem I'm having is that the FInt control registers (hardware config.) only have the option of 24KHz, which doesn't seem to be available in the sampling rate control box in the tool bar. Likewise the 32KHz option in the sampling rate control box in the tool bar isn't available in the interpolator. Is there a way round this please?
Just bumping this - title should have read ADAU1787, sorry but I didn't notice that due to the large page header and it won't let me edit the title. This is quite important AD, we will be moving to an alternative DSP if this problem isn't solveable, and it does look like it's a SigmaStudio issue.
Hi Dunmail,
Based on the description of the issue setting up 24K for SDSP is simpler option.
For setting the sample rate for SDSP to 24k, can be done by right clicking the SDSP input cell. See the Figure below. in this cell I am using Serial Port as Input for SDSP. You need to do this for the input cell used in your design. Then enter the value of 24000 in the cell.
Similarly ensure the FDSP sample rate is set to 768K by right clicking the FDSP input cell in SStudio schematic.
The Interpolator can then be used to interpolate the sample rate from 24K to 768K using the FINT register Tab. Make sure the FINT is included in your SStudio schematic for FDSP as one of the inputs. I have used FINT0 as an example.
The interpolator block does not support 32K explicitly. But since you are ok with setting 24K for SDSP, I hope this should help solve the issue you are facing. However if 32K for SDSP is required then we will need more information on your project and then could suggest some more options.
Regards
Rajeev
Hi Rajeev Thanks for getting back to me on this matter. I'd already set the FDSP and SDSP clock rates as you describe, but when I go to compile I get a bucket full of errors all basically saying that loads of processes are set to operate at 32K (as per the sample rate window in the toolbar I presume) which is incompatible with 24K - is there something I need to set to fix this please?
And by the way 24K is OK for the SDSP - it's doing mostly "side chain" processing so full audio bandwidth isn't really necessary. 32KHz would be better, but for now 24K will do.
OK, so I managed to sort out the errors - there were quite a few other things (e.g. DC sources) apart from the inputs that needed the sampling frequency setting manually before it would compile. However though it now sort of works, the audio quality is not the best, if it's possible to enable 32K to 384K upsampling then that will likely make it better. I can give you more information about the project Rajeev but it will need to be done privately as there's a patent application involved.
Any news on this please Rajeev?
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