ADAU1452, Serial Port, Master Mode syncronous
Hi,
I have an odd requirement.
I am using an ADAU1452 (SigmaStudio V4.6) and I want two of the output serial ports to generate their own output clocks on LRCLK_OUT0(1) and BCLK_OUT0(1) pins; but I want the LRCLK to be in phase with an LRCLK that I am providing on LRCLK_OUT2. Is this possible?
I think I have to set the ports as Master Mode in SugmaStudio for them to generate the clocks on the pins as outputs but then that doesn't allow me to select the ports to be "slave to a clock domain".
Is there a way that I could write to any registers after the program is loaded to change configuration for sync'ing without turning off the pins as outputs?
I know that the DATA_OUT from sigmaDSP will be in sync with the clocks generated by the sigmaDSP but for other reasons I would like to have all LRCLK signals to be matching phase if possible.
Thanks for any help
PhilipJ
PS: The reason is that we didn't have enough pins on our FPGA to drive all the clocks to all the devices so I said to my hardware designer, "Oh thats all right I can drive the DAC clocks directly from the sigmaDSP!!" Famous last words...
Audio Signal Processors
adau1452
SigmaDSP Audio Processors
Hello Phillip,
It is an easy misunderstanding to make. I wish it were possible but it is not. You can drive the data out from any of the clocks but the slave input cannot be routed to an actual pin output. Only the internal sources can be sent out of the pin when it is set to be a master. Clock generator 3 has an external input but every time I have used it the clock output is not good. So the only way to do this for you is to actually jumper the pins externally.
If all the DACs are oversampling DACs, then the phase difference should be really small. It will be less than one sample period to start with but it will be different every time it is powered up from cold. I am assuming both clock sources are using the same master clock? Then the difference will be the time it takes to initialize and start the dividers for the clocks. That is where the variability will come from. I really wish there had been a clock reset of some sort to start the counters all at the same time.
Dave T
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