Sport does not accept data in the processor  ADSP-SC589

processor ADSP-SC589

In the example below, outputs half SPORT1_A go to the inputs half SPORT1_B.

Used mode: DSP standard and DMA disabled

clock SPORT1_A = 1 Mhz;

It is necessary for sport to output 16 bits of data that would accompany 16 clocks and a frame in "late frame sync, active low" mode.

The example shown below implements this variant of the sport port setting.
In this example, the receive buffer SPORT1_B remains empty and the interrupt does not work!

If the GCLKEN bit is changed to 0 in the SPORT1_CTL_A register (Gated Clock disable), SPORT1_B will start to receive data and the interrupt will work.

How to receive data in SPORT1_B when SPORT1_CTL_A.GCLKEN = 1 ?

//----------- Interrupt handler SPORT1_B ---------------

void int_SPORT1_reseive_b0(uint32_t iid, void *handlerArg){
int temp0;
temp0 = *pREG_SPORT1_RXPRI_B; //receive bufer
}

//***********************************************************************

//***********************************************************************

void SportInit(void){

//----------- config SPORT1_A ---------------
*pREG_SPORT1_CTL_A = 0x022374F1;
*pREG_SPORT1_CTL2_A = 0x0;
*pREG_SPORT1_DIV_A = 0x000F00E0;

//----------- config SPORT1_B ---------------

*pREG_SPORT1_CTL_B = 0x002330F1;
*pREG_SPORT1_CTL2_B = 0x0;

//----------- Connect outputs half SPORT1_A as inputs half SPORT1_B ---------------
SRU(SPT1_AFS_O,SPT1_BFS_I);
SRU(SPT1_ACLK_O,SPT1_BCLK_I);
SRU(SPT1_AD0_O,SPT1_BD0_I);

//----------- Register interrupt ---------------
adi_int_InstallHandler(INTR_SPORT1_B_DMA,int_SPORT1_reseive_b0,0,true);

//------------ transmit DATA -----------------

*pREG_SPORT1_TXPRI_A = 0xaaaa;

//----------------------------------------------------

return;
}

Audio Signal Processors

adsp-sc589

SHARC Audio Processors/SoCs