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ADSP-SC589 DDR3 size

Processors & DSP roneng Aug 30, 2016 00:00 1 replies Original on forum ↗
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roneng Question
Aug 30, 2016 00:00

I have a custom board with SC589 processor.

On board I have a DDR3 memory of size = 4Gb.

I created a custom pre-load project (copy of sc589 preload project that comes with cross-core) and changed the DMC0/DMC1 configuration parameter DDR_SIZE to 4G.

I tried the custom preload program. The preload executes with no errors but the DDR is not functioning properly and the ARM core project cannot be executed from the DDR3 memory.

I also tried to run the SHARC core1 DDR test program (from POST project) and it fails.

Which parameters in the DMC controller I need to change to support my DDR3 chip except for the DDR_SIZE?

The DDR3 chip I am using is ISSI IS43TR16256AL-125KBL,

Thanks,

Ronen

Audio Signal Processors

adsp-sc589

SHARC Audio Processors/SoCs

roneng Reply
Sep 7, 2016 00:00

Problem solved by modifying DMC timing registers and DMC control register values.

Created a custom preload program for core0 using the modified values.

Ronen