SPORT Frame sync edge detection mode

Hello Ren,

When SPORT is configured for late frame syncs mode, the first bit of the transmit data word is available and the first bit of the receive data word is sampled in the same serial clock cycle that the frame sync is asserted. In multichannel operation, this is the case when frame delay is 0. Receive data bits are sampled by serial clock edges, but the frame sync signal is only checked during the first bit of each word. Internally generated frame syncs remain asserted for the entire length of the data word in late framing mode. Externally generated frame syncs are only checked during the first bit.

The below figure illustrate the difference between late and early frame sync modes

Thanks,

Jithul

Hi Jihul,

Thanks for the reply.

what you've mentioned is mostly focused on my last question, so I'm still looking for answers for my other questions.

Just on my last question, i still don't have a very clear understanding.

when you say "Externally generated frame syncs are only checked during the first bit".

how does the SPORT receive controller determine "the first bit"? SLEN counter reaches zero?

is it ok to have frame sync period larger than word width? i.e. extra SCLK with no data before the next frame sync.

would this be a problem or would the SPORT receive controller always treat the data sampled at the SCLK edge after the next frame sync signal to be the first bit of the next word, regardless of the number of extra SCLK cycles at the end of the previous frame.

thanks

Ren

Hi Ren,

To make more clear on the statement, "Externally-generated frame syncs are only checked during the first bit", for SPORT in late frame sync mode once the processor detects the first frame sync they do not need to be asserted after that time period and it is ok that you can have the frame sync period larger than word width. Once the first entire word has been transmitted (or received) the SPORT controller transmit data or received data only when the next frame sync is asserted.

Note that the Internally-generated frame syncs remain asserted for the entire length of the data word in late framing mode

Is this answers your query?

Thanks,

Jithul

Hi Jithul,

Yes this answers my second question, but just to clarify the device behavior.

for edge detection, external, receiving, late frame sync,what happens if the frame sync edge arrived earlier, before SLEN reaches zero?

would the frame sync signal be ignored, or would the reviving controller recolonize the next sampled data to be the first bit of the next word?

the example shown in Figure 29-5 (page 1364) of the ADSP-SC58x SHARC Processor Hardware Reference manual has shown that for the case of early frame sync, an early arrival frame sync signal will be ignored, is this the same for late frame sync?

Also, i'm still looking for the answer for my first question, which is, for edge detection, external, receiving, late frame sync,does it matter where the other edge of the frame sync signal is?

e.g. if the falling edge of the FS signal is used, is there any timing dependency between the rising edge of the FS and the data width?

thank you.

Ren

Please let me know which processor exactly you are reffing to?

Hi Jithul,

For me, the question is really "which ADI DSP can support my interface?".

I am looking at ADSP-SC58x SHARC Processor, but the question extend to other (relatively recent) ADI DSPs.

Do the SPORT interfaces on different ADI DSPs behave differently?

Maybe let me ask the question another way, refer to the diagram in my original post.

if my ADC's data interface outputs CLK, FS and DATA as shown in the diagram, with DATA timing following DATA B or DATA C, if any/all of the ADI DSP's SPORT interface can be configured to receive data from my ADC?

Ren

Hi Ren,

Sorry for delay in response on this. The implementation of SPORT module in ADSP-SC58x is slight different from other old SHARC Processor (ADSP-214xx, ADSP-213xx etc), but similar to newer Blackfin processors(BF60x, BF70x etc). The SPORT top module in ADSP-SC58x consists of two half SPORTs with identical functionality. Each SPORT half can be independently configured as either a transmitter or receiver and can be coupled with the other HSPORT within the same SPORT. However SPORT module in old SHARC processor has two bidirectional channels (A and B) per serial port, configurable as either transmitters or receivers. Each serial port can also be configured as two receivers or two transmitters, permitting two unidirectional streams into or out of the same serial port (Full duplex is not possible using one SPORT). Having said that SPORT functionality in all DSPs are more or less identical.

if my ADC's data interface outputs CLK, FS and DATA as shown in the diagram, with DATA timing following DATA B or DATA C, if any/all of the ADI DSP's SPORT interface can be configured to receive data from my ADC?

>> It should be possible to interface all of ADI DSP's SPORT to receive data from DAC.

Thanks,

Jithul

Thanks Jithul for coming back to me on this.

Anyway the sake of others wondering about the same thing, we've done some test with the blackfin part (BF70x).

Case B works with late frame sync, but the main problem is, with FS configured as level detection, the FS will be triggered again at end of the word. the SPORT controller will stop reeving data only after FS has gone high.

this creates issue as the DSP will need to deal with a lot of rubbish data created by the extra clock cycles.

ideally late frame sync with edge detection will work for case B, but edge detection is not supported on older DSPs, newer ones like ADSP-SC58x do support it.

for level detection FS, it's better to use early frame sync.

for the signal shown in case B, the early frame sync will not check for FS again until the full word has been received, so as long as the FS width is less than the word length, you don't have to worry about the rubbish data.

the only problem with early FS is it start to receive 1xSCLK after the FS being sampled, so if the FS width is longer than 1xSCLK, delay is required. this problem can be addressed by using multi-channel mode (available on most DSPs) and in which a n-SCLK delay between MSB and FS can be programmed.

Ren