Question about TDM mode(or packed mode) on ADSP-21489
Thread Summary
The user inquires about the ADSP-21489's support for 64-channel TDM using SPORT0 and SPORT1, the generation of Bit Clock and FS, and the feasibility of high Bit Clock rates. The final answer confirms that each SPORT supports up to 128 channels, PCG is the best option for generating Bit Clock and FS, and the maximum serial port clock frequency is fPCLK/4 in master transmitter mode and fPCLK/8 in slave transmitter mode. The user is advised to check the ADSP-21489 datasheet and the ADSP-214xx SHARC Processor Hardware Reference manual for detailed timing specifications.AI Generated Content
Hi,
In a design based on 21489, I try to use sport0 A channel as 64-channel TDM sender and sport1 A channel as 64-channel TDM receiver. SPORT0 receive audio data of TDM from FPGA. The sampling frequency of I2S is 48kHz, and CLKIN on this ez-board is 25MHz. I would like to ask some questions .
1. I want to confirm whether each SPORT(A or B) supports up to 128 channels or not ? Or,both the serial data A and B channels of each sport supports up to 128 channels ?
2. Is the only way to generate Bit Clock and FS by using PCG ? PCG input clock selection is from oscillator(12.288MHz) on my ez-board.
3. I use packed I2S mode and 64-channel TDM, then how to calculate the value of Bit Clock and FS ? Maybe the value of Bit Clock is more than 100MHz,so I would like to know the feasibility of TDM data transmission between FPGA and DSP in
such a high Bit Clock .
I am also looking for some relevant example code.
So any one can give me some suggestions on these problems?
Many thanks!
Audio Signal Processors
adsp-21489
processors and dsp
Processors and Microcontrollers
SHARC Audio Processors/SoCs
Hello,
1. I want to confirm whether each SPORT(A or B) supports up to 128 channels or not? Or,both the serial data A and B channels of each sport supports up to 128 channels ?
>> In ADSP-21489 Serial Port (SPORT) up to 128 channels are available for transmitting or receiving or both. Each SPORT can receive or transmit data selectively from any of the 128 channels.
2. Is the only way to generate Bit Clock and FS by using PCG ? PCG input clock selection is from oscillator(12.288MHz) on my ez-board.
>>This processors have eight independent Serial ports (SPORT0 to SPORT7). Each SPORT has its own set of control registers and data buffers and SPORT configured as master can generate clocks and frame syncs internally. The fundamental timing clock of the SPORT modules is peripheral clock/4 (PCLK/4). Each serial port has a clock signal (SPORTx_CLK) for transmitting and receiving data on the two associated data signals. The clock and frame sync signals are configured by the ICLK/IFS and CLKDIV/FSDIV bits of the SPCTLx/DIVx control registers. One clock signal clocks both A and B data signals (either configured as inputs or outputs) to receive or transmit data at the same rate.
PCG is the best option in the processor to provide Bit Clock and FS externally to the SPORT.
3. I use packed I2S mode and 64-channel TDM, then how to calculate the value of Bit Clock and FS ? Maybe the value of Bit Clock is more than 100MHz,so I would like to know the feasibility of TDM data transmission between FPGA and DSP in
such a high Bit Clock .
>> In slave transmitter mode and master receiver mode, the maximum serial port frequency is fPCLK/8. In master transmitter mode and slave receiver mode, the maximum serial port clock frequency is fPCLK/4. To determine whether communication is possible between two devices at clock speed n, the following
specifications must be confirmed:
1) frame sync delay and frame sync setup and hold;
2) data delay and data setup and hold; and
3) SCLK width.
Please look into the SPORT timing specification mentioned in the ADSP-21489 datasheet.
Also, I would suggest you to refer the Serial ports (SPORTs) chapter mentioned in the ADSP-214xx SHARC Processor Hardware Reference manual, it can be downloaded here.
Regards,
Jithul
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