ADAU1466 SDATA_OUTx Clock Output

I am trying to line up clocks and data on an SDATA_OUTx port that matches incoming clocks on LRCLK_IN/OUT0 and BCLK_IN/OUT0.

My understanding is when any SDATA_OUTx port needs to be a BCLK and LRCLK master it has to use one of the 3 clock generators to do so and cannot slave directly to incoming clocks that serve the clock domains 0-3, is this correct? What I have tried doing to line them up is to use clock generator 3 (CLK GEN3) that uses a FREF from my incoming LRCLK that I am trying to match up with. In this case I am using MP10. However when doing this the BLCK and SDATA_OUT is still not quite lined up with the incoming BCLK however much closer than when using CLK_GEN1 What I have been using to verify the alignment is comparing the BCLK coming into the DSP on BLCK_IN and the associated BCLK_OUT and it's alignment with the SDATA_OUT when the BCLK_OUT is set as master.

I wanted to see if I am going about this the right way or if there might be another way to do this so that I can better source the SDATA_OUTx master clocks (BCLK/LRCLK) directly with my incoming clock. Didn’t know if there was another way to skin this like with using the ASRC’s but I don’t see how that would improve the serial audio clocking.

Audio Signal Processors

SigmaDSP Audio Processors

adau1466