SIMD mode with starting address that is odd

Question -- we are discussing SIMD memory operations of the form

//SIMD Stuff Starts

bit set MODE1 PEYEN;

nop;

nop;

lcntr = R12, do (pc, _SIMD_Address_Test_Loop_End) until lce;

F1 = dm(I4, 2);

dm(I5, 2) = F1;

SIMD_Address_Test_Loop_End:

nop;

nop;

nop;

//SIMD Stuff Ends

bit clr MODE1 PEYEN;

nop;

nop;

On 21469 -- it does not seem to matter whether i4 starts even and increments by 2 or starts odd and increments by 2

Has it ever mattered on any SHARC (going back to 20161) whether the dual memory access starts with odd or even address?

Or is there a hidden CCES default setting that activates a DAB in newer SHARC processors?

I know that it is an issue on TigerSHARC in Q{ ] or L[ ] mode unless the DAB is activated with Visual DSP

Thanks

Mike Smith

sharc

memory corruption

simd