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BF518F16 cache init

Processors & DSP mantur Aug 6, 2015 00:00 2 replies Original on forum ↗
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mantur Question
Aug 6, 2015 00:00

I developed a board based on BF518F16 with 64Mbyte SDRAM and 8Gbyte NAND.

All work fine, but would like to know where can I find a document or an example code where explained the cache initialization and usage.

I use the GNU toolchain with a homebuilt environment:

Blackfin GNU Toolchain - D.T.A.

In a simple SDRAM speed test I achieve a performance of 170 Mbyte/s in writing and 30 Mbyte/s in reading.

Can be these value increased with a correct cache initialization?

Regards

Manuele

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gvasanth Reply
Aug 26, 2015 00:00

Sorry for the late reply.

EE-271 explains the cache concepts in detail. Can you please look at it available in the below link:

http://www.analog.com/media/en/technical-documentation/application-notes/EE-271_Rev2.pdf

http://www.analog.com/media/en/technical-documentation/application-notes/EE271v02.zip

Regards,

Guru

EZAdministrator Reply
Aug 2, 2018 00:00

This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

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EZ Admin