SSM2603 Device Driver and VisualDSP

Hi Gireesh,

Please accept my sincere apology for the delay in response. If power on self test was able to successfully configure codec, then Device Driver code should have worked as well. I believe you are referring to below example of VDSP installation,

ADSP-BF518F_EZKIT-Rel1.0.0\BF518F_EZ-Board\Blackfin\Examples\AudioLoopback

The only thing I suspect is adi_ssl_init.c. Have you changed ASYNC,SDRAM, CLKIN parameters of this file with accordance to custom board?

Thanks,

Sachin

Hi Sachin,

The file adi_ssl_init.c which is working fine for uart application has been utilised for SSM2603 application. In uart application I hasn't encountered any problem. I am facing problem only in SM2603 application. I am attaching the setting in adi_ssl_init.c file

ADI_EBIU_ASYNCH_CLKOUT clkout_enable = ADI_EBIU_ASYNCH_CLKOUT_ENABLE;

/* which banks to enable */

ADI_EBIU_ASYNCH_BANK_ENABLE banks_enable = ADI_EBIU_ASYNCH_BANK0_1_2_3;

/* bank timing parameters - specified in cycles */

/* transition times for the four banks */

ADI_EBIU_ASYNCH_BANK_TIMING asynch_bank_trans_time = {ADI_EBIU_BANK_ALL, { ADI_EBIU_ASYNCH_TT_4_CYCLES, { 0, ADI_EBIU_TIMING_UNIT_NANOSEC } } };

/* time between Read Enable assertion to de-assertion */

ADI_EBIU_ASYNCH_BANK_TIMING asynch_bank_read_access_time = { ADI_EBIU_BANK_ALL, { 0xB, { 0, ADI_EBIU_TIMING_UNIT_NANOSEC } } };

/* time between Write Enable assertion to de-assertion */

ADI_EBIU_ASYNCH_BANK_TIMING asynch_bank_write_access_time = { ADI_EBIU_BANK_ALL, { 7, { 0, ADI_EBIU_TIMING_UNIT_NANOSEC } } };

/* time from beginning of memory cycle to R/W-enable */

ADI_EBIU_ASYNCH_BANK_TIMING asynch_bank_setup_time = { ADI_EBIU_BANK_ALL, { ADI_EBIU_ASYNCH_ST_3_CYCLES, { 0, ADI_EBIU_TIMING_UNIT_NANOSEC } } };

/* time from de-assertion to end of memory cycle */

ADI_EBIU_ASYNCH_BANK_TIMING asynch_bank_hold_time = {ADI_EBIU_BANK_ALL, { ADI_EBIU_ASYNCH_HT_2_CYCLES, { 0, ADI_EBIU_TIMING_UNIT_NANOSEC } } };

/* specify whether ARDY enabled (is used to insert extra wait states) */

ADI_EBIU_ASYNCH_BANK_VALUE asynch_bank_ardy_enable = { ADI_EBIU_BANK_ALL, { ardy_enable: ADI_EBIU_ASYNCH_ARDY_DISABLE } };

/* specify whether ARDY is sampled low or high */

ADI_EBIU_ASYNCH_BANK_VALUE asynch_bank_ardy_polarity = { ADI_EBIU_BANK_ALL, { ardy_polarity: ADI_EBIU_ASYNCH_ARDY_POLARITY_LOW } };

ADI_PWR_COMMAND_PAIR ezkit_power[] = {

{ ADI_PWR_CMD_SET_PROC_VARIANT,(void*)ADI_PWR_PROC_BF512SBBC1400 }, /* 400Mhz ADSP-BF526 */

{ ADI_PWR_CMD_SET_PACKAGE, (void*)ADI_PWR_PACKAGE_LQFP }, /* in MBGA packaging, as on all EZ-KITS */

{ ADI_PWR_CMD_SET_VDDEXT, (void*)ADI_PWR_VDDEXT_330 }, /* external voltage supplied to the voltage regulator is 3.3V */

{ ADI_PWR_CMD_SET_VDDINT, (void*)ADI_SSL_EXT_VDDINT }, /* Externally supplied VDDINT (see adi_ssl_Init.h)*/

{ ADI_PWR_CMD_SET_CLKIN, (void*)25 }, /* the CLKIN frequency 25 MHz */

{ ADI_PWR_CMD_END, 0 } /* indicates end of table */

};

ADI_EBIU_TIMING_VALUE twrmin = {1,{7500, ADI_EBIU_TIMING_UNIT_PICOSEC}}; // set min TWR to 1 SCLK cycle + 7.5ns

ADI_EBIU_TIMING_VALUE refresh = {8192,{64, ADI_EBIU_TIMING_UNIT_MILLISEC}}; // set refresh period to 8192 cycles in 64ms

ADI_EBIU_TIME trasmin = {44, ADI_EBIU_TIMING_UNIT_NANOSEC}; // set min TRAS to 44ns

ADI_EBIU_TIME trpmin = {20, ADI_EBIU_TIMING_UNIT_NANOSEC}; // set min TRP to 20ns

ADI_EBIU_TIME trcdmin = {20, ADI_EBIU_TIMING_UNIT_NANOSEC}; // set min TRCD to 20ns

u32 cl_threshold = 100; // set cl threshold to 100 Mhz

ADI_EBIU_SDRAM_BANK_VALUE bank_size = {0, {size: ADI_EBIU_SDRAM_BANK_32MB }}; // set bank size to 32MB

ADI_EBIU_SDRAM_BANK_VALUE bank_width = {0, {width: ADI_EBIU_SDRAM_BANK_COL_9BIT}}; // set column address width to 9-Bit

ADI_EBIU_COMMAND_PAIR ezkit_ram[] = {

{ ADI_EBIU_CMD_SET_SDRAM_BANK_SIZE, (void*)&bank_size },

{ ADI_EBIU_CMD_SET_SDRAM_BANK_COL_WIDTH,(void*)&bank_width },

{ ADI_EBIU_CMD_SET_SDRAM_CL_THRESHOLD, (void*)cl_threshold },

{ ADI_EBIU_CMD_SET_SDRAM_TRASMIN, (void*)&trasmin },

{ ADI_EBIU_CMD_SET_SDRAM_TRPMIN, (void*)&trpmin },

{ ADI_EBIU_CMD_SET_SDRAM_TRCDMIN, (void*)&trcdmin },

{ ADI_EBIU_CMD_SET_SDRAM_TWRMIN, (void*)&twrmin },

{ ADI_EBIU_CMD_SET_SDRAM_REFRESH, (void*)&refresh },

/* Asynch Commands memory controller commands */

{ ADI_EBIU_CMD_SET_ASYNCH_CLKOUT_ENABLE, (void*)&clkout_enable },

{ ADI_EBIU_CMD_SET_ASYNCH_BANK_ENABLE, (void*)&banks_enable },

{ ADI_EBIU_CMD_SET_ASYNCH_BANK_TRANSITION_TIME, (void*)&asynch_bank_trans_time },

{ ADI_EBIU_CMD_SET_ASYNCH_BANK_READ_ACCESS_TIME, (void*)&asynch_bank_read_access_time },

{ ADI_EBIU_CMD_SET_ASYNCH_BANK_WRITE_ACCESS_TIME, (void*)&asynch_bank_write_access_time },

{ ADI_EBIU_CMD_SET_ASYNCH_BANK_SETUP_TIME, (void*)&asynch_bank_setup_time },

{ ADI_EBIU_CMD_SET_ASYNCH_BANK_HOLD_TIME, (void*)&asynch_bank_hold_time },

{ ADI_EBIU_CMD_SET_ASYNCH_BANK_ARDY_ENABLE, (void*)&asynch_bank_ardy_enable },

{ ADI_EBIU_CMD_SET_ASYNCH_BANK_ARDY_POLARITY, (void*)&asynch_bank_ardy_polarity },

{ ADI_EBIU_CMD_END, 0 }

};

With regards

Gireesh.M

Hi Gireesh,

Can you provide more details about the failure, does read write to SSM codec happens successfully through TWI/SPI interface?

Sachin

Hi Sachin,

Thanks for the reply,

I am abale to read and write to SSM2603 through the code given in Power In self test.

Once Iam trying to access SSM2603 through the driver I am encountering probelm with error code 0x4000017.

With regards

Gireesh.M

Hi Girish,

0x4000017 corresponds to TWI locked error. It is possible that some TWI device on the bus is pulling it low or Codec is not acknowledging to address or TWI prescale values and clock dividers are not properly programmed to generate 100KHz clock.

Thanks,
Sachin

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