how to choose the sample rate of ADC?

Hello Wei Jl,

First of all I need to know a little more about the clocking but I will make some assumptions. The assumption is that the AD1939 is using the internal PLL and is the master for the ADC outputs.

The sample rates are divided down from the master clock (MCLK) input. The setting for 32/44.1/48 kHz is setting an internal divider from the MCLK. The EZ board comes with a 12.288 MHz MCLK oscillator. It is U12 on the board. Dividing this by 256 will give you the 48 kHz you are seeing. It is quite simple to obtain 32 kHz fs with this MCLK frequency. All you need to do is change the divider in the PLL. Right now the PLL and Clock Control Register 0, (address 0x00) bits 2:1 will be set to 00 giving you the 256 x fs divider. Change this to "01" and you will divide this by 384 which will give you 32 kHz fs.

44.1 kHz however is a problem. It is not an integer division of 12.288 Mhz so the only way to get 44.1 kHz is to change the frequency of the MCLK to 11.289600 MHz which is 256 x fs. There is another way, the AD1939 is capable of operating as a slave using only LRCLK as a clock source for the PLL. So you would have to have the SHARC send out the LRCLK. The problem with that is the loop filter components will need to be changed on the evaluation board. C259, C258 and R461. Consult the codec datasheet for details on the values. If you have to run at 44.1 kHz then it may be easier to just change out the oscillator module.

Let me know if you need further assistance.

Dave T

Dear DaveThib,

Many thanks for your advice, I'll try the methods you mentioned.