How does overlay PACKING works?

Hello Yves.

The PACKING command specifies how to interpret the 32-bit storage data when packing three reads into two 48-bit instructions.Assuming your storage order is accurately reflected in the PACKING command you provided (i.e., B3, B4, B5, B6, B11, B12, B1, B2, B7, B8, B9, B10), then the resolved byte-order for two 48-bit instructions would be:

B1, B2, B3, B4, B5, B6

B7, B8, B9, B10, B11, B12

-Joe

Hello Jobo23,

Thank you for this answer but I also read pages 3-45 to 3-50 from the Linker and Utilities Manual. Your answer does not answer my question. I would like to understand what B3 or B4 means with clear examples.

In Table 3-4 page 3-47, there is an example of DMA packing order. I can read that

B1 and B2 are bit 47 to 32 from word 1. So I guess I can write description of Bx as a C struct

struct {

B1:8

B2:8

B3:8

B4:8

B5:8

B6:8

B7:8

B8:8

B9:8

B10:8

B11:8

B12:8

}

The mentioned transfer order is:

B1

B2 //< First transfer done

B3

B4 //< First transfer done

(B0)

B11

B12 //< Third transfer done

B5

B6

(B0)

B7

B8

B9

B10

(B0)

It says after the third transfer the unpacked order are

B1, B2, B3, B4, B5, B6.

I don't understand thi. B5 ans B6 were not already transfered. Also How the packing logic knows which Bx to swap?

Also we notice the B0 which is not described in this document. Could you explain what is it?

In my project I have this PACKING which is not described neither in the ADI library or in the Linker User Manual. With the documents I have read. I cannot understand this packing below works.

I would like to get an answer to it.

PACKING(12 B3 B4 B5 B6 B0\

B11 B12 B1 B2 B0\

B7 B8 B9 B10 B0)

Hi Yves.

The linker/loader automatically care for the byte placement for the source memory, and ADI has a bunch of EE-Notes for overlay management with examples, depending on which SHARC you are using (as there are some differences)...for the ADSP-21371 that you indicated, I think EE-220 is the one:

http://www.analog.com/media/en/technical-documentation/application-notes/EE-220.pdf

I believe the external port on the 371 is the same as the the 26x and 36x processors discussed in this note. It was the 375 that changed the external port bus width; however, I am more of a Blackfin guy and would give way to a SHARC expert...if you haven't seen this app note, give it a look and see if it helps. Regarding your last question, I don't see documentation anywhere as to the meaning of B0, but it appears to simply be a NULL byte in the app notes (depending on where actual data is for the cases where it is a 16-bit external access), but unless there is an assumption that it is 40-bit data all the time for overlays, I have no idea why it there in this case...

-Joe

Hi ,

For overlay packing data is always considered to be 40 bit. When you are placing the data in 32 bit memory you basically make the last byte as 0 using byte B0 for the least significant byte of 40 bit.

Now when you are placing the following 2 Program instruction (12 bytes) in 32 bit data space.

B1 B2 B3 B4 B5 B6

B7 B8 B9 B10 B11 B12

The Packing instruction always consider 5 bytes for data. Since you are placing the above 2 instruction in 32 bit space, the fifth byte is B0 representing 0 ( and is ignored) and the actual instructions bytes are placed in 32 bit space as follows. Basically you start picking from the least significant byte from the instructionand start placing it sequentially starting from the least significant byte in the 32 bit space

Packing (12 B3 B4 B5 B6 B0\

B11 B12 B1 B2 B0\

B7 B8 B9 B10 B0 )

Hope this clarifies.