BF592 not reaching main after SPORT interrupt

Processors & DSP spetca Feb 13, 2015 00:00 1 replies Original on forum ↗

spetca Question

Feb 13, 2015 00:00

I am setting up SPORT0 Interrupts as such:

void Init_Interrupts(void)

{

*pSIC_IMASK0 |= IRQ_DMA2 | IRQ_DMA1;

*pSIC_IAR1 |= 0xfffff23f ;

register_handler(ik_ivg9, SPORT0_Tx_ISR);

register_handler(ik_ivg10, SPORT0_Rx_ISR);

*pIMASK |= EVT_IVG9 | EVT_IVG10;

ssync();

}

Then later I enable

void SPORT0_Enable(void)

{

*pSPORT0_TCR1 |= TSPEN ;

// *pSPORT0_RCR1 |= RSPEN;

ssync();

}

and it correctly interrupts to this routine. However while watching registers the DMA2_IRQ_STATUS register never toggles after it gets to the end of this isr, it steps to the last ssync() in the enable function above and interrupts again.

EX_INTERRUPT_HANDLER(SPORT0_Tx_ISR)

{

*pDMA2_IRQ_STATUS |= 0x0001;

ssync();

*pSPORT0_TX16 = 0xafaf;

}

trying to do some processing in main() and it will not reach outside the enable and interrupt ISR

bf592

interrupt

sport

blackfin

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jobo23 Reply

Mar 16, 2015 00:00

The interrupt request from the SPORT is asserted as long as there is room in the FIFO. Given you are loading directly to the SPORT_TX register, I am assuming you are not using DMA, therefore the interrupt will be asserted as soon as you enable the SPORT (which is what you are seeing). However, you are clearing the interrupt request prior to loading data, so clearing the interrupt request will have no effect on the hardware because you still have not loaded the FIFO, so the hardware will reassert the interrupt immediately. Your TX FIFO for 16-bit data is 8 deep, so you'd need to write the SPORT_TX register 8 times to completely fill the FIFO. The HRM provides guidance regarding not causing an overflow so that you can control how software loads the FIFO:

"To find out whether the core processor can access the SPORT_TX register without causing this type of error, read the register’s status first. The TXF bit in the SPORT_STAT register is 0 if space is available for another word in the FIFO."

-Joe

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