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tMDCIH timing for Bf527

Processors & DSP wallman16 Jul 28, 2010 00:00 2 replies Original on forum ↗
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wallman16 Question
Jul 28, 2010 00:00

Hi ,

Please let me know with regards timing for MDC in Ethernet .

BF527

MDC Rising Edge to MDIO Input Invalid (Hold) Min =10ns ,

page 69 - 70

http://www.analog.com/static/imported-files/data_sheets/ADSP-BF522_BF523_BF524_BF525_BF526_BF527.pdf

PHY on BF527 EZ-KIT

MDC to MDIO (Read from PHY) delay Min is 0ns

Page 55

http://www.smsc.com/media/Downloads_Public/Data_Sheets/8700.pdf

should we have to use buffer of 10 ns between PHY and BF527 .

Thanking you

With best regards and wishes

JoeT Reply
Aug 2, 2010 00:00

This issue is being handled over private support so I am locking it.

-Joe

EZAdministrator Reply
Aug 2, 2018 00:00

This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

Thank you,
EZ Admin