Time from POWER_ENABLE0 to stabilization of SOP clock (BCLK / LRCLK) on ADAU1452

Hello HTCV3,

I will make the assumption that the part has powered up and the PLL is locked and the initialization code has run and the part has been programmed. That will all affect the time for the clocks to appear.

So I am assuming that you are disabling the power to the serial ports at some point then reenabling them?

The power enables are simply the clocks being gated to those sections of the part. With no clocks the section of the part will draw a lot less current. So if the serial port is already been configured and had been operating when the serial port was disabled, then it will stop what it is doing when the power enable is shut off. It will hold its position of what it was doing at the time. Then when the power is enabled it will continue exactly where it left off.

So this means that the data may be corrupted and the first frame will be a partial frame. Then at the end of the frame it will pick up the current sample(s) and continue from there. So it will take up to one sample period before you will get one complete frame with current data. So wait one sample period as a minimum.

Dave T