External oscillator with ADAU1701 and multiple I2C codecs

Hello Daniel,

I agree that using a clock/osc chip is the best way to provide an MCLK. This way someone else has already chosen the proper crystal and support circuitry to get it to oscillate reliably. They are not that expensive and yes, most of them will have the drive strength to drive several parts. I do not have one to recommend but there are so many to choose from. Just check their drive strength but I am guessing most will do it. You could also use a clock distribution chip or several low noise buffers to distribute the clock to each chip.

So I would send the clock to all three chips and save MP11 for other uses.

The PCB layout, Yes keep the traces short and minimize the vias in your layout. It is also good to have a damping resistor for each destination. The value really should be determined by using signal integrity simulation tools to see what value will give the best performance. Generally these resistors are in the range of 10-50ohms. 33 ohms is a common value.

Dave T

Perfect, good to know. I will do some research and see what oscillator will suit my needs!

I realized shortly after posting this that I would be using MP11 for the i2s bit clock output, so that was a no-go from the start anyhow.

When you say to minimize vias, is that in general/including stuff to the ground and power planes? Or just if I were to pass signals from one layer to another? I plan to only have my top layer for analog and digital signals and the other three layers for ground, 3v3 and 5v respectively. I also don't know yet if I will be using a copper pour on the top layer for anything; I have seen designs that use it for 1.8 and 3.3 volts (1.8 closest to the chip, 3v3 surrounding)... Is there any benefit or recommendation for that?

Now, as far as distributing LRCLK and BCLK to different IC's go - In my current design with the 1701 I have three IC's that need these, one ADC and two DAC's. I have read elsewhere that it may be a good idea to use a clock distribution/buffer IC for these as well? From what I understand, it isn't recommended to have a fanout of these from the master to several slaves, and unlike the 14xx chips the 1701 only has one set of LRCLK and BCLK in and out connections.

Thanks!

Daniel

An update:

I found this older thread:

RE: ADAU1701 - BCLK & LRCLK Distribution

This seems to have given me the answer I needed on BLCK and LRCLK distribution! Seeing the data provided in the thread, I think I am confident with going without a clock buffer and just doing a fanout with the appropriate damping resistors in place. I will of course keep traces as consistent in length as possible. Will help cut cost and complexity down.

Daniel

Hello Daniel,

You win the forum member of the day award for doing a great job in searching the forum for an answer!

Regarding your questions about the vias and power planes etc.

Designs are all about tradeoffs. You do need to have the ground plane on layer 1. Regarding power planes, It is a good idea. I always look at the placement of the parts and highlight all the pins for the power nets and look at where they are verses the source of the power. Then I try to see where the current will be flowing and place the planes in a way where there is a good path for the current. Hard to describe since it is a visualization thing and very creative. You can spring for fancy power integrity software I suppose. So I try not to block other pins from a different power plane. So for the split power plane it is a creative process.

For the top layer, I have seen plenty of copper fills tied to ground on the top layer. I have done it many times and not done it many times. The only little detail is with the planes under a part and if it has a EP on the bottom of the part. For an EP you need to use many vias to the ground plane but keep the ground pins on the part from connecting to the ground fill under the part. This has caused issues before. Look at the ADAU1452 Datasheet way near the end of the datasheet is a PCB considerations section and example layouts. Look at how the bypass caps are connected to the part and where the vias are to get to the power and ground planes. Try your best to do it like that such that the trace from the ground pin HAS to pass by the bypass cap on the way to ground. This will allow the cap to be much more effective. This is why you do not let the ground pins attach to the top layer fill or the EP until it has gone by the bypass cap.

Your other question about the vias and clock lines. Yes, I was not talking about vias to power planes, you need those but for vias that go from layer to layer. You want to minimize those because the inductance of the via and the abrupt direction change will cause ringing and possibly RF emissions. So this is why i said to minimize them. On evaluation boards we usually have headers and test points and things like that which is not great but must be there. So again, it is about tradeoffs.

Thanks,

Dave T

Dave,

Got it, thanks for the response! I've been soaking in as much information as I can from this forum in hopes to better my design and understand what I am dealing with (for context, I am quite new to PCB design as a whole and have been diving deep). As of right now, I am just working on prototypes.

I ended up revising my design further, replacing the three IC's with just one codec (PCM3168), making things much simpler. The datasheet for my codec of choice recommends a copper pour for ground (It also has an EP with vias required, as do two TPA3118 IC's in my design), but I am not so sure I want to have the pour extend to the area with the 1701 and its circuitry.* Would there be any issues with having the copper pour only cover a certain area on the top layer but span the entire board on the inner ground layer?

In regards to a split power plane, my plan as of now is to do it as such, though my codec does not allow for a split of 3.3 and 5 volts with a straight divide (QFP with 3.3v and 5v on two opposing sides and more 5v on the other opposing sides). I will definitely need to get creative with that one!

Thankfully, I was able to avoid running my master clock through any via's but had to run a few i2s serial audio data lines to the bottom layer as well as BCLK and LRCLK to the codec. I would have liked to keep them on the top layer but given the pin placement of both IC's I wasn't too sure how to make that happen. Maybe I could move some analog audio paths to go to the bottom layer through via's instead? Not too sure.

Would you mind taking a look at my schematic/PCB layout to make sure there isn't anything super wrong with it? I feel like my component placement isn't the prettiest but should serve its purpose. Also whether or not my routing i2s stuff through via's to the bottom layer is workable or needs revised. I also am a bit unsure about my use of the CMOS crystal oscillator, and don't know if anything besides damping resistors is needed on its output to the two IC's. I've tried searching for information elsewhere on how to use them properly, but have come up a bit short.

Thanks,

Daniel

*EDIT: I didn't want to include the pour on the ADAU1701 side of things because I forgot how to isolate the ground tracks that go from the IC pins to the bypass caps, but that was just a dumb moment... I can just change the net of those specific traces/pins/pads to something new like "GND_ISO" and Bob's your uncle.