ADAU 1787 TDM IN/OUT

Here are my Sigma DSP folders :

TDM16OUT.zip

Thanks for the file.

I do have some more questions before I get too deep into your project.

What are the desired serial format you are using?

The processor is sending the clock.

Bit clock frequency?

LRCLK/Frame Clocks frequency? This should be 44.1kHz and from your screenshot it looks like it is a pulse format.

What is the desired bit depth you want?

What is the number of bits that you want in each channel slot?

How many channels do you want to send?

Your earlier screenshot of the scope did show four channels of data. I could use a larger picture.

Oh! one more thing. Is this processor expecting the data to be delayed by one bit clock period at the start of the frame or no delay?

Dave T

Objective : We wish to make the ADAU send TDM 16bit 16 channels at 44.1kHz

Current status: We are starting from a TDM 16 bits 16 channels at 44.1 kHz project that we know works. We therefore wish to make such a setup work before moving on to any other configuration.

TDM16 from Processor to ADAU: Currently we have managed to send audio from our processor to the ADAU without our processor's master clock being linked to the ADAU's MLCK I was surprised to be able to do that without using the ASRCI, but perhaps I read the docs wrong.

TDM16 from ADAU to Processor: This is where our setup does not work. No matter the settings we put in the ADAU we get no signal back on the SPT1_OUT (checked with oscilloscope). We have confirmed that the SDSP is active by sending a sine out on the DAC (headphones emit the correct sine wave), but when connected to SPT1, we get just get a 0V and no data. Can the ADAU send 16 out while receiving 16 in on a single serial port?

DaveThib said:
What are the desired serial format you are using?

We want to use TDM16 IN and OUT. Here is a screenshot of channel 0, 2, 4, 6 being used resulting in a zeros between each active channels

DaveThib said:
The processor is sending the clock.

Yes, it's sending BCLK and LRCLK, if needed it can also send MCLK although it is not connected as of now.

DaveThib said:
Bit clock frequency

Currently with our setup the BCLK frequency is 16 bit * 16 channels * 44.1 kHz so 11.3 MHz which was verified experimentally with an oscilloscope (11.26 MHz on the picture).

DaveThib said:
LRCLK/Frame Clocks frequency?

The LRCLK issued by our processor is a TDM FSync signal that is a one-bit wide pulse at a frequency of 44.10 kHz which is what we have on our oscilloscope. Our signal seems to follow the datasheet (p.57).

DaveThib said:
What is the desired bit depth you want?

What is the number of bits that you want in each channel slot?

How many channels do you want to send?

Could you define the difference between bit depth and number of bits?

Currently we wish to send 16 bits 16 channel TDM at 44.1 kHz, the processor is sending this 16 bit, 16 channel TDM. Received by the ADAU correctly.

DaveThib said:
Is this processor expecting the data to be delayed by one bit clock period at the start of the frame or no delay?

The ADAU currently receives TDM16 data from our processor using the I2S setting for SPT1_DATA_FORMAT in TDM mode (not sure what that means regarding the delay), but we are able to play the received data on the DAC confirming this works correctly.

Thanks a lot in advance,

Best regards,

Valentin

Hi,

We changed our setup, we connected the MCLK beetween our processor and our ADAU.
We can now send serial data from or ADAU but we're having unrelated hardware difficulties.
We are tring to deal with those.

Thank you very much.

Hello Val52100,

Sorry I have been busy and not able to respond. What are the difficulties you are dealing with now?

Glad you worked out the serial port issues.

Dave T