TDM8 DAC with external generator on 1452

generator is used 24576 and the DAC (CS42438) takes 256fs

Hello ABanditoz,

What frequency is the external master clock set to?

Can you attach your project. There are many things that can cause issues and it is much faster for me to look through the project.

I also need to know your hardware schematic to see which pins are connected to the DAC.

Also, do you have an oscilloscope? I suggest you look at the Frame ( LRCLK ) clock, bit clock and SDATA pins to see what is coming out of or into the DSP. You also did not mention who is going to be the clock master for the TDM signals?

Thanks

Dave T

Hi Dave,

The project frequency is 96kHz. How do I send you the files? I have an oscilloscope, I will send you a photo later. The master for TDM is an external oscillator, because from it comes the MCLK signal for the DAC

Hello ABanditoz,

The easiest way to attach the files onto a post is to drag and drop the file into the reply window. You could use the "Insert" pull down but it is a little bit more of a process to do it.

So the external oscillator provides the MCLK but where is the bit clock and LRCLK ( Frame clock ) coming from?

So you are using TDM8 at 96kHz and I assume a 32 bit channel slot. So that means your bit clock will be 24.576MHz so I assume your master clock will be the same correct?

So somewhere you are developing the frame clock.

Dave T

Design 1.dspprojPDF

--So the external oscillator provides the MCLK but where is the bit clock and LRCLK ( Frame clock ) coming from? ---

From 1452

--So you are using TDM8 at 96kHz and I assume a 32 bit channel slot. So that means your bit clock will be 24.576MHz so I assume your master clock will be the same correct? --

Yes

TDM output port SDATAOUT0

Hello ABanditoz,

It looks like you did a great job of setting up the part with one setting that somehow was changed from the default.

The clock generator setting that selects the clock source for the serial port was set to Clock Generator 3. For your application just set it to Clock Generator 1 and you will be fine.

I cannot fully test your project easily here since you are running on a 24MHz clock and the eval boards are not setup for TDM8 but I am confident this will make the difference.

I checked your fs setting in the project,

Then I checked your core strt pulse and that was set to 96kHz.

I checked the PLL and it was setup correctly for a 24.576MHz master clock.

The clock generator 1 was setup properly. By the way, Clock generator 3 was setup for the default 44.1kHz base fs. Since you had the 2*fs setting the serial port was putting out 88.2kHz fs and if the codec/DAC requires a precise 256x fs master clock then it will not see it as valid and mute. Because your 256x clock was running for a 96kHz fs.

So you were SO close to getting it all correct.

Give this a try.

Thanks,

Dave T

Hi Dave.Thanks for the tip, but unfortunately no luck, no sound. I can provide a clipping from the datasheet, what i2s sending is needed, maybe in this regard tips on how to set up properly.

Hello ABanditoz,

OK, So you want that TDM format where the LRCLK is a positive going pulse? No problem, this is what you do:

Dave T