ADAU1463/67 no SDATA Output on Slave Channels
Hello all,
i'm using an ADAU1463 as 8ch I2S Output as follows:
- Serial Output Clock Domain0 is Master, SDATA_OUT0 carries 2 Signals (L/R)
- Serial Outputs 1 - 3 are all set as slaves to Clock Domain0, each of the SDATA_OUTx Pins shall output 2 Signals (L/R).
--> Please see attached screenshots
Serial Out0 outputs a SDATA_Signal as it should, but no other channel outputs any digital Signal on the Pins (52/57 & 60). This changes only if i also set the corresponding LRCLK-Signal as Master, the DSP not put out any signal if it is not set to Master-LRCLK for each channel.
Per Datasheet, this seems like unintended behaviour, as Page54 in the datasheet suggest the Serial Outputs can be used in slave mode to LRCLK0.
Any help here?
Thanks alot already!
ADAU1463_TestSW_V1.dspproj
Audio Signal Processors
adau1452
adau1467
i2s
adau1463
adau145x
SigmaDSP Audio Processors
SigmaDSP
adau1466
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Hey all,
meanwhile i found this thread from a while ago: https://ez.analog.com/dsp/sigmadsp/f/q-a/547501/adau1452-sdata_out3-slave-to-clk-domain-0-does-not-work/427250#
It seems to be intended you have to set the corresponding ports as Masters if you want them to act as actual output (from the same clock), setting them as slaves to domainX does not work as one would expect on the first glance. As stated in the Thread, the LRCLK Pins can still be used as GPIOs even if they are set as Masters in the I2S-Port. (And the I2S-Outputs will be in Sync with the other ports, if they run from the same clock)
Therefore it should work to for example send Data to an AD1937 using all I2S-Ports set as described, and not using the SDATAIO Pins on all Ports.
Would be great if someone from analog can confirm my theory for the '1463, i will try and verify this in the Lab too this week!
Thanks!
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