Power-on Require timing sequence between Reset ne-gate and Audio clock input start (ADSP-21569)

Hi Masa Hibino,

Please refer the Clock and Reset Timing (Pg No: 55/104) in the ADSP-2156x Datasheet. The link is given below.
www.analog.com/.../adsp-21562-21563-21565-21566-21567-21569.pdf

Could you please let us know what you mean by ne-gate?

Regards,
Divya.P

Dear Divya,

Thank you for your reply.

But, I didn't mean SYS_CLKIN but "Clock input timing using for AUDIO e.x. Frame clock, Bit clock".

Could you re-answer to me about this issue?

BR,
Masa Hibino

Hi Masa Hibino,

Sorry for the inconvenience. Did you mean timing between the reset and bit clock,frame clock. Please correct us if our understanding is wrong. if it is right means its input timing depends upon the enabling the bits of the corresponding registers (ex: sports).

Regards,
Anand Selvaraj.

Dear Anand,

I meant the timing between the reset negate and starting to supply frame clock and bit clock to the DSP.

Sorry, I can't understand the meaning of "the enabling the bits of the corresponding registers (ex: sports).....

Who decide the timing demand between the reset negate and starting to supply frame clock and bit clock to DSP? Which has to be earlier them? Is this related the setting of the registers???

BR,
Masa Hibino

Hi Masa Hibino,

SYS_HWRST Deasserted after VDD_SUPPLIES (VDD_INT , VDD_EXT, VDD_DMC, VDD_REF,VDD_ANA) and SYS_CLKIN0 are Stable and Within Specification. If you are using frame clock and bit clock of the serial port(sport) in the DSP. You need to set corresponding registers for enabling the sport in your projects otherwise sport doesn't produce bit clock and frame clock.

Regards,
Anand Selvaraj.

No, I don't use internal bit and frame clock.

But, I add bit and frame clock from external circuit.

When this design condition, could you tell me the timing spec of the timing between SYS_HWRST deasserted and starting to add external bit and frame clock.

BR,
Masa Hibino

Hi Masa Hibino,

SYS_HWRST Deasserted after VDD_SUPPLIES and SYS_CLKIN0 are Stable. So you can add the external bit and frame clock after the SYS_HWRST deasserted.

Regards,
Anand Selvaraj.

Your answer confuse me.

What is the spec? Which design is needed?

I need detail numerical spec.

Can anyone who is Analog Devices Engineer answer about this issue???

Hi Masa Hibino,

This issue is already handled through private support. To avoid duplication of efforts,You can the continue the discussions through private support and final resolution here if appropriate.

Regards,
Anand Selvaraj.