PCG trigger mode reset

Processors & DSP THarris716 Oct 12, 2022 00:00 1 replies Original on forum ↗

Thread Summary

The user is experiencing issues with I2S clock and frame sync signals not re-synchronizing to an external periodic event after the first cycle when using the PGC in trigger mode. The final answer suggests checking the External Event Trigger Delay in the ADSP-21569 Hardware Reference Manual and asks for details on the clock source and probe image. The solution requires ensuring the PGC is configured to re-sync on each trigger event.
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THarris716 Question

Oct 12, 2022 00:00

I am trying to construct I2S clock and frame sync by using the PGC in trigger-mode, hoping to synchronize to an external periodic event.

The very first cycle, the signals are generated as advertized -- 2.5 - 3.5 cycles (of internal sys clk) after the event, both FS and clock transition.

However, thereafter, they just free run while ignoring the trigger.

Is there a way to make it always re-sync to the trigger, any time the event occurs?

I don't see this addressed in the documentation.

hardware

sharc

CCES 2.9.3.0

ADSP-2156x

trigger mode

pcg

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ADIApproved Reply

Oct 14, 2022 00:00

Hi,

We suggest to refer the External Event Trigger Delay (Page no:1138/2331). The link for the ADSP-21569 Hardware Reference Manual is given below.
www.analog.com/.../adsp-2156x_hwr.pdf

Can you please provide your comments on the below points.
1. For our understanding, Are you using a Internal or external Clock?
2.Can you please give the details in probe image, which one is Clock Input , External Trigger Input and Frame Sync(Output)?

Thanks,
Anand Selvaraj.

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