When to use PLL vs MCLK?

Hello bklein,

You actually have asked several questions here so I need to give you several responses.

In this part the PLL only is there to produce a frequency of roughly 24MHz. The output is then divided by 2 to obtain the 12.288MHz clock for the core and the converters. But it does depend on how fast you want to run the core. Let me paste in this diagram from SigmaStudio:

If you do not have a master clock that is fast enough in your design or want to use some other clock you might have in your system then you need to use the PLL to bring it up to a frequency that is evenly divisible by 48kHz if that is your desired rates for the internal clocks. Actually, in this part you probably would run at 192kHz but the register settings all refer to 48k as a base rate.

In the case that you can select a 12.288MHz crystal then you might not need the PLL. In this part when you use the PLL you need to divide the output by 2 and feed a 12.288MHz clock to the core and system blocks. When you do not use the PLL you can change the dividers to divide by 1 and run a clock directly into the core and other system blocks from the 12.288MHz signal coming into the MCLKIN pin.

One of the advantages of the PLL is to smooth out any jitter in the clocks.

Then you asked about using the APx555. Well, when interfacing to and from an external system using the serial port, the master clock is not needed because the serial ports use sample rate converters. The ASRC will convert from the input rate to the internal rate and back. There is no need to feed the part a synchronous clock, it can be running with its own crystal and the ASRC will convert over to the internal clock domain. This is a really powerful feature. It allows the external device to change sample rates, or if the sample rate slowly drifts it does not matter. The ASRC will follow it. This is why this part has been very popular for applications like conference phones and radios where there is no way to send an actual master clock because the audio is going over a network or being transmitted over the airwaves. There is no need to recover the clock or to stop and change sample rates, the part will just follow.

To make the most of this I would always suggest you run the ADAU1772 serial ports as a clock slave so the APx555 would be the master for the LRCLK and BCLK and it will use its own MCLK and not need to feed it to the ADAU1772.

Your question about multiple codecs, Yes, one way is to feed the clock from this one over to the others but if the others are this part or the ADAU372 then you may not have to. I would have to see the entire system block diagram to help you with this.

Dave T

Thanks, I had more help from AP plus I figured some of this out.